View IS43TR16640A_6501984.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 1 rev. 00a 04/16/2012 128mx8, 64mx16 1gb ddr3 sdram advanced information april 2012 features ? standard voltage: v dd and v ddq = 1.5v 0.075v low voltage (l): v dd and v ddq = 1.35v + 0.1v, -0.067v ? high speed data transfer rates with system frequency up to 933 mhz ? 8 internal banks for concurrent operation ? 8bits pre-fetch architecture ? programmable cas latency: 5, 6, 7, 8, 9, 10 and 11 ? programmable additive latency: 0, cl-1,cl-2 ? programmable cas write latency (cwl) based on tck ? programmable burst length: 4 and 8 ? programmable burst sequence: sequential or interleave ? bl switch on the fly ? auto self refresh(asr) ? self refresh temperature(srt) ? refresh interval: 7.8 us (8192 cycles/64 ms) tc= -40c to 85c 3.9 us (8192 cycles/32 ms) tc= 85c to 105c ? partial array self refresh ? asynchronous reset pin ? tdqs (termination data strobe) supported (x8 only) ? ocd (off-chip driver impedance adjustment) ? dynamic odt (on-die termination) ? driver strength : rzq/7, rzq/6 (rzq = 240 ? ) ? write leveling ? operating temperature: commercial (t c = 0c to +95c) industrial (t c = -40c to +95c) automotive, a1 (t c = -40c to +95c) automotive, a2 (t c = -40c to +105c) options ? configuration: 128mx8 64mx16 ? package: 96-ball fbga (9mm x 13mm) for x16 78-ball fbga (8mm x 10.5mm) for x8 address table parameter 128mx8 64mx16 row addressing a0-a13 a0-a12 column addressing a0-a9 a0-a9 bank addressing ba0-2 ba0-2 page size 1kb 2kb auto precharge addressing a10/ap a10/ap bl switch on the fly a12/bc# a12/bc# speed bin speed option 187f 15g 15h 125j 125k 107k 107l units jedec speed grade ddr3- 1066f ddr3- 1333g ddr3- 1333h ddr3- 1600j ddr3- 1600k ddr3- 1866k ddr3- 1866l cl-nrcd-nrp 7-7-7 8-8-8 9-9-9 10-10-10 11-11-11 11-11-11 12-12-12 tck trcd,trp(min) 13.125 12.0 13.5 12.5 13.75 11.77 12.84 ns note: faster speed options are backward compatible to slower speed options. copyright ? ? ? 2011 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c . ) ? pote n t i a l ? li ab ili ty ? o f ? in teg r ated ? s ili co n ? so l ut i o n , ? in c ? i s ? adequate l y ? p r otected ? u n de r ? t h e ? c ir cu m sta n ces
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 2 rev. 00a 04/16/2012 1. ddr3 package ballout 1.1 ddr3 sdram package ballout 78-ball fbga ? x8 1 2 3 4 5 6 7 8 9 a vss vdd nc nu/tdqs# vss vdd b vss vssq dq0 dm/tdqs vssq vddq c vddq dq2 dqs dq1 dq3 vssq d vssq dq6 dqs# vdd vss vssq e vrefdq vddq dq4 dq7 dq5 vddq f nc 1 vss ras# ck vss nc g odt vdd cas# ck# vdd cke h nc cs# we# a10/ap zq nc j vss ba0 ba2 nc(a15) vrefca vss k vdd a3 a0 a12/bc# ba1 vdd l vss a5 a2 a1 a4 vss m vdd a7 a9 a11 a6 vdd n vss reset# a13 nc(a14) a8 vss note: nc balls have no internal connection. nc(a14) and nc(a15) are one of nc pins and reserved for higher densities. 1.2 ddr3 sdram package ballout 96-ball fbga ? x16 1 2 3 4 5 6 7 8 9 a vddq dqu5 dqu7 dqu4 vddq vss b vssq vdd vss dqsu# dqu6 vssq c vddq dqu3 dqu1 dqsu dqu2 vddq d vssq vddq dmu dqu0 vssq vdd e vss vssq dql0 dml vssq vddq f vddq dql2 dqsl dql1 dql3 vssq g vssq dql6 dqsl# vdd vss vssq h vrefdq vddq dql4 dql7 dql5 vddq j nc vss ras# ck vss nc k odt vdd cas# ck# vdd cke l nc cs# we# a10/ap zq nc m vss ba0 ba2 nc(a15) vrefca vss n vdd a3 a0 a12/bc# ba1 vdd p vss a5 a2 a1 a4 vss r vdd a7 a9 a11 a6 vdd t vss reset# nc(a13) nc(a14) a8 vss note: nc balls have no internal connection. nc(a1 3), nc(a14) and nc(a15) are one of nc pins and reserved for higher densities .
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 3 rev. 00a 04/16/2012 1.3 pinout description - jedec standard symbol type function ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. cke, (cke0), (cke1) input clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self- refresh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for self-refresh exit. after vr efca and vrefdq have become stable during the power on and initialization sequence, they must be maintained during all operations (including self-refresh). cke must be maintained high th roughout read and write accesses. input buffers, excluding ck, ck#, odt and cke, are disabl ed during power-down. input buffers, excluding cke, are disabled during self-refresh. cs#, (cs0#), (cs1#), (cs2#), (cs3#) input chip select: all commands are masked when cs # is registered high. cs# provides for external rank selection on systems with multiple ranks. cs# is considered part of the command code. odt, (odt0), (odt1) input on die termination: odt (registered high) enab les termination resistance internal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqsu, dqsu#, dqsl, dqsl#, dmu, and dml signal. the odt pin will be ignored if mr1 and mr2 are programmed to disable rtt. ras#. cas#. we# input command inputs: ras#, cas# and we# (along with cs#) define the command being entered. dm, (dmu), (dml) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. for x8 device, the function of dm or tdqs/tdqs# is enabled by mode register a11 setting in mr1. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write, or precharge command is being applied. bank address also determines which mode register is to be accessed during a mrs cycle. a0 - a13 input address inputs: provide the row address for active commands and the column address for read/ write commands to select one location out of t he memory array in the respective bank. (a10/ap and a12/bc# have additional functions; see below) . the address inputs also provide the op-code during mode register set commands. a10 / ap input auto-precharge: a10 is sampled du ring read/write commands to determine whether autoprecharge should be performed to the access ed bank after the read/write operation. (high: autoprecharge; low: no autoprecharge). a10 is sampled during a precharge command to determine whether the precharge applies to one ba nk (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by bank addresses. a12 / bc# input burst chop: a12 / bc# is sampled duri ng read and write commands to determine if burst chop (on-the-fly) will be performed. (high, no burst chop; low: burst chopped). see command truth table for details. reset# input active low asynchronous reset: reset is active when reset# is low, and inactive when reset# is high. reset# must be high during normal operation. reset# is a cmos rail- to- rail signal with dc high and low at 80% and 20% of vdd, i.e., 1.20v for dc high and 0.30v for dc low. dq input / output data input/ ou tput: bi-directional data bus. dqu, dql, dqs, dqs#, dqsu, dqsu#, dqsl, dqsl# input / output data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. for the x16, dqsl corresponds to the data on dql0-dql7; dqsu corresponds to the data on dqu0-dqu7. the dat a strobes dqs, dqsl, and dqsu are paired with differential signals dqs#, dqsl#, and dqsu#, respectively, to provide differential pair signaling to the system during reads and writes. ddr3 sdram s upports differential data strobe only and does not support single-ended. tdqs, tdqs# output termination data strobe: tdqs/tdqs# is applicable for x8 drams only. when enabled via mode register a11 = 1 in mr1, the dram will en able the same termination resistance function on tdqs/tdqs# that is applied to dqs/dqs#. w hen disabled via mode register a11 = 0 in mr1, dm/tdqs will provide the data mask functi on and tdqs# is not used. x4/x16 drams must disable the tdqs function via mode register a11 = 0 in mr1. nc no connect: no internal electrical connection is present. vddq supply dq power supply: 1.5 v +/- 0.075 v for stand ard voltage or 1.35v +0.1v, -0.067v for low voltage vssq supply dq ground
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 4 rev. 00a 04/16/2012 vdd supply power supply: 1.5 v +/- 0.075 v for standar d voltage or 1.35v +0.1v, -0.067v for low voltage vss supply ground vrefdq supply reference voltage for dq vrefca supply reference voltage for ca zq, (zq0), (zq1), (zq2), (zq3) supply reference pin for zq calibration input only pins (ba0-ba2, a0-a13, ras#, cas#, we#, cs#, cke, odt, and reset#) do not supply termination.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 5 rev. 00a 04/16/2012 2. function description 2.1 simplified state diagram abbreviation function abbreviation function abbreviation function act active read rd, rds4, rd s8 pde enter power-down pre precharge read a rda, rdas4, rdas8 pdx exit power-down prea precharge all write wr, wrs4, wrs8 sre self-refresh entry mrs mode register set write a wra, wras4, wras8 srx self-refresh exit ref refresh reset start reset procedure mpr multi-purpose register zqcl zq calibration long zqcs zq calibration short power on power applied reset from any state reset procedure initialization zqcl zq calibration zqcl zqcs idle mrs,mpr, write levelin g self refresh sre srx ref refreshing precharge power down pdx pde act activating bank active active power down pde pdx reading writing writing reading precharging automatic sequence command sequence write write write a write write a write a pre,prea read read a read read a pre,prea pre,prea read a read
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 6 rev. 00a 04/16/2012 2.2 reset and initialization procedure 2.2.1 power-up initialization sequence the following sequence is required for power up and initialization. 1. apply power (reset# is recommended to be maintained below 0.2 x vdd; all other inputs may be undefined). reset# needs to be maintained for minimum 200 us with stable power. cke is pulled low? anytime before reset# being de-asserted (min. time 10 ns). the powe r voltage ramp time between 300mv to vdd(min) must be no greater than 200 ms; and during the ramp, vdd > vddq and (vdd - vddq) < 0.3 volts. ? vdd and vddq are driven from a single power converter output, and ? the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. in addition, vtt is limited to 0.95 v max once power ramp is finished, and ? vref tracks vddq/2. or ? apply vdd without any slope reversal be fore or at the same time as vddq. ? apply vddq without any slope reversal before or at the same time as vtt & vref. ? the voltage levels on all pins other than vdd, vddq, vss, vssq must be less than or equal to vddq and vdd on one side and must be larger than or equal to vssq and vss on the other side. 2. after reset# is de-asserted, wait for another 500 us until cke becomes ac tive. during this time, the dram will start internal state initialization; this will be done independently of external clocks. 3. clocks (ck, ck#) need to be started and stabilized for at least 10 ns or 5 tck (which is larger) before cke goes active. since cke is a synchronous signal, the corresponding set up time to clock (tis) must be met. also, a nop or deselect command must be registered (with tis set up time to clock) before cke goes active. once the cke is registered ?high? after reset, cke needs to be continuously registered ?high? until the initialization sequence is finished, including expiration of tdllk and tzqinit. 4. the ddr3 sdram keeps its on-die termination in high-im pedance state as long as r eset# is asserted. further, the sdram keeps its on-di e termination in high impedance state after reset# deassertion unt il cke is registered high. the odt input signal may be in undefined state unt il tis before cke is registered high. when cke is registered high, the odt input signal may be statically held at either low or high. if rtt_nom is to be enabled in mr1, the odt input signal must be statically held low. in all cases, the odt input si gnal remains static until the power up initialization sequence is finished, in cluding the expiration of tdllk and tzqinit. 5. after cke is being registered high, wait minimum of reset cke exit time, txpr, before issuing the first mrs command to load mode register. (txpr=max (txs ; 5 x tck) 6. issue mrs command to load mr2 with all application se ttings. (to issue mrs command for mr2, provide ?low? to ba0 and ba2, ?high? to ba1.) 7. issue mrs command to load mr3 with all application se ttings. (to issue mrs command for mr3, provide ?low? to ba2, ?high? to ba0 and ba1.) 8. issue mrs command to load mr1 with all application settings and dll enabled. (to issue "dll enable" command, provide "low" to a0, "high" to ba0 and "low" to ba1 ? ba2). 9. issue mrs command to load mr0 with all application se ttings and ?dll reset?. (to issue dll reset command, provide "high" to a8 and "low" to ba0-2).
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 7 rev. 00a 04/16/2012 10. issue zqcl command to starting zq calibration. 11. wait for both tdllk and tzqinit completed. 12. the ddr3 sdram is now ready for normal operation. figure2.1.1 reset and initialization sequence at power-on ramping 2.2.2 reset initialization with stable power the following sequence is r equired for reset at no power interruption initialization. 1. asserted reset below 0.2 * vdd any time when reset is needed (all other inputs may be undefined). reset needs to be maintained for minimum 100 ns. cke is pulled ?low ? before reset being de-asserted (min. time 10 ns). 2. follow power-up initialization sequence steps 2 to 11. 3. the reset sequence is now completed; dd r3 sdram is ready for normal operation. ta ck,ck# vdd,vddq reset# cke cmmand ba odt rtt tb t=200s tmin=10ns t=500s tcksrx tis tis tis ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) tc td ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) txpr tmrd tmrd tmrd tmod tzqinit tdllk tis valid valid valid valid mrd mrd mrd mrd zqcl 1) mr 2 mr 3 mr 1 mr 0 ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) te tf tg th ti tj tk note1. from time point td? until ?tk? nop or des commands must be applied between mrs and zqcl commands. time brea k don?t care static low in case rtt_nom is enabled at time tg, otherwise static high or low 1)
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 8 rev. 00a 04/16/2012 figure2.1.2 reset procedure at power stable condition 2.3 register definition 2.3.1 programming the mode registers for application flexibility, various functi ons, features, and modes are programmable in four mode registers, provided by the ddr3 sdram, as user defined variables and they mu st be programmed via a mode register set (mrs) command. as the default values of the mode registers (mr#) are not def ined, contents of mode register s must be fully initialized and/or re-initialized, i.e. written, after power up and/or reset for proper operation. also t he contents of the mode registers can be altered by re-executing the mrs command during normal operation. when programmi ng the mode registers, even if the user chooses to modify only a sub-set of the mrs fields , all address fields within the accessed mode register must be redefined when the mrs command is issued. mrs comma nd and dll reset do not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents the mode register set command cycle time, tmrd is required to complete the writ e operation to the mode register and is the minimum time required between two mrs commands shown as below. ta ck,ck# vdd,vddq reset# cke cmmand ba odt rtt tb t=100ns tmin=10ns t=500s tcksrx tis tis tis ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) tc td ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) txpr tmrd tmrd tmrd tmod tzqinit tdllk tis valid valid valid valid mrd mrd mrd mrd zqcl 1) mr 2 mr 3 mr 1 mr 0 ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ) te tf tg th ti tj tk note1. from time point td? until ?tk? nop or des commands must be applied between mrs and zqcl commands. time brea k don?t care static low in case rtt_nom is enabled at time tg, otherwise static high or low 1)
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 9 rev. 00a 04/16/2012 figure2.3.1a tmrd timing the mrs command to non-mrs command delay, tmod, is requi re for the dram to update the features except dll reset, and is the minimum time required from an mrs command to a non-mrs command excluding nop and des shown as the following figure. figure 2.3.1b tmod timing the mode register contents can be changed using the same command and timing requirements during normal operation as long as the dram is in idle state, i.e., all banks are in the precharged state with trp satisfied, all data bursts are completed and cke is high prior to writing into the mode register. if the rtt_nom feature is enabled in the mode register prior and/or after an mrs command, the odt signal must continuously be registered low ensuring rtt is in an off state prior to the mrs command. the odt signal may be registered high after tmod has expired. if the rtt_nom feature is disabled in the mode register prior and after an mrs command, the odt signal can be registered either low or high before, during and after the mrs command. the mode registers are divided into various fields depending on the functionality and/or modes. ck# ck command address cke settings odt odt rtt_nom enabled prior and/or after mrs command rtt_nom disabled prior and after mrs command odtloff + 1 old settings ( ( ) ) time brea k don?t care valid valid valid valid valid valid valid valid valid valid valid valid mrs valid valid nop/ dec valid valid valid valid mrs valid valid valid valid valid valid valid valid valid valid valid valid nop/ dec nop/ dec nop/ dec tmrd tmrd new settings ck# ck command address cke settings odt odt rtt_nom enabled prior and/or after mrs command rtt_nom disabled prior and after mrs command odtloff + 1 old settings ( ( ) ) time brea k don?t care valid valid valid valid valid valid valid valid valid valid valid valid mrs valid valid nop/ dec valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid nop/ dec nop/ dec nop/ dec tmod new settings nop/ dec
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 10 rev. 00a 04/16/2012 2.3.2 mode register mr0 the mode register mr0 stores the data for controlling various operating modes of ddr3 sdram. it controls burst length, read burst type, cas latency, test m ode, dll reset, wr and dll control for precharge power-down, which include vendor specific options to make ddr3 sdram useful for vari ous applications. the mode register is written by asserting low on cs#, ras#, cas#, we#, ba0, ba1, and ba2, while cont rolling the states of address pins according to the following figure. 1. a13 must be programmed to 0 during mrs. 2. wr (write recovery for autoprecharge)min in clock cycles is calculated by dividing twr(in ns) by tck(in ns) and rounding up to the next integer: wrmin[cycles] = roundup(twr[ns] / tck[ns]). the wr value in the mode register must be programmed to be equal or larger than wrm in. the programmed wr value is used with trp to determine tdal. 3. the table only shows the encodings for a given cas latency. for actual supported cas latency, please refer to speedbin table s for each frequency 4. the table only shows the encodings for write recovery. for act ual write recovery timing, please refer to ac timing table. figure 2.3.2 ? mr0 definition 2.3.2.1 burst length, type and order accesses within a given burst may be programmed to sequential or interleaved order. the burst type is selected via bit a3 as shown in figure 2.3.2. the ordering of accesses within a burst is determined by the bur st length, burst type, and the starting column address as shown in table below. the burst lengt h is defined by bits a0-a1. burst length options include fixed bc4, fixed bl8, and ?on the fly? which allows bc4 or bl8 to be selected coincident with the registration of a read or write command via a12/bc#. ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 0 0 0* 1 ppd wr dll tm cas latency rbt cl bl mode register 0 a8 dll reset a7 mode a3 read burst type a1 a0 bl 0 n o 0 n omal 0 n ibble sequential 0 0 8 (fixed) 1 yes 1 test 1 interleave 0 1 bc4 or 8 (on the fly) 1 0 bc4 (fixed) a12 dll control for write recovery for autoprecharge 11 reserved precharge pd a11 a10 a9 wr(cycles) 0 slow exit (dll off) 0 0 0 16 *2 a6 a5 a4 a2 cas latency 1 fast exit (dll on) 00 1 5 *2 0 0 0 0 reserved 01 0 6 *2 0 010 5 ba1 ba0 mr select 0 1 1 7 *2 0 100 6 00 mr0 10 0 8 *2 0 110 7 01 mr1 10 1 10 *2 1 000 8 10 mr2 11 0 12 *2 1 010 9 11 mr3 11 1 14 *2 1 100 10 1 1 1 0 11 0 001 12 0 011 13 0 101 14 0 1 1 1 15 1 0 0 1 16 1 0 1 1 reserved 1 1 0 1 reserved 1 1 1 1 reserved
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 11 rev. 00a 04/16/2012 burst length read/ write starting column address (a2,a1,a0) burst type = sequential (decimal) a3 = 0 burst type = interleaved (decimal) a3 = 1 notes 4 chop read 0 0,1,2,3,t,t,t,t 0,1, 2,3,t,t,t,t 1, 2, 3 1 1,2,3,0,t,t,t,t 1,0, 3,2,t,t,t,t 1, 2, 3 10 2,3,0,1,t,t,t,t 2,3, 0,1,t,t,t,t 1, 2, 3 11 3,0,1,2,t,t,t,t 3,2, 1,0,t,t,t,t 1, 2, 3 100 4,5,6,7,t,t,t,t 4,5, 6,7,t,t,t,t 1, 2, 3 101 5,6,7,4,t,t,t,t 5,4, 7,6,t,t,t,t 1, 2, 3 110 6,7,4,5,t,t,t,t 6,7, 4,5,t,t,t,t 1, 2, 3 111 7,4,5,6,t,t,t,t 7,6, 5,4,t,t,t,t 1, 2, 3 write 0,v,v 0,1,2,3, x,x,x,x 0,1,2,3,x,x, x,x 1, 2, 4, 5 1,v,v 4,5,6,7, x,x,x,x 4,5,6,7,x,x, x,x 1, 2, 4, 5 8 read 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 2 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6 2 10 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5 2 11 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4 2 100 4,5,6,7,0, 1,2,3 4,5,6, 7,0,1,2,3 2 101 5,6,7,4,1, 2,3,0 5,4,7, 6,1,0,3,2 2 110 6,7,4,5,2, 3,0,1 6,7,4, 5,2,3,0,1 2 111 7,4,5,6,3, 0,1,2 7,6,5, 4,3,2,1,0 2 write v,v,v 0,1,2, 3,4,5,6,7 0,1,2, 3,4,5,6,7 2, 4 notes: 1. in case of burst length being fixed to 4 by mr0 setting, t he internal write operation starts two clock cycles earlier than f or the bl8 mode. this means that the starting point for twr and twtr will be pulled in by tw o clocks. in case of burst length being selected on-the-fly via a12/bc#, the internal write operation starts at the same point in time like a burst of 8 write operation. this means that during on-the-fly control, the starting point for twr and twtr will not be pulled in by two clocks. 2. 0...7 bit number is value of ca[2:0] that c auses this bit to be the first read during a burst. 3. t: output driver for data and strobes are in high impedance. 4. v: a valid logic level (0 or 1), but res pective buffer input ignor es level on input pins. 5. x: don?t care. 2.3.2.2 cas latency the cas latency is defined by mr0 (bits a9-a11) as shown in figure 2.3.2. cas latency is the delay, in clock cycles, between the internal read command and the availability of t he first bit of output data. ddr3 sdram does not support any half-clock latencies. the overall read latency (rl) is defined as additive latency (al) + cas latency (cl); rl = al + cl. for more information on the supported cl and al settings based on the operating clock frequency, refer to ?standard speed bins?. 2.3.2.3 test mode the normal operating mode is selected by mr0 (bit a7 = 0) and all other bits set to the desired values shown in figure 2.3.2. programming bit a7 to a ?1? places the ddr3 sdram into a test mode that is only used by the dram manufacturer and should not be used. no operations or functionality is specified if a7 = 1. 2.3.2.4 dll reset the dll reset bit is self-clearing, meaning that it returns ba ck to the value of ?0? after the dll reset function has been issued. once the dll is enabled, a subsequent dll reset sh ould be applied. any time that the dll reset function is used, tdllk must be met before any functions that requi re the dll can be used (i.e., read commands or odt synchronous operations). 2.3.2.5 write recovery the programmed wr value mr0 (bits a9, a10, and a11) is used for the auto precharge feature along with trp to determine tdal. wr (write recovery for auto-precharge) min in clock cycles is calculated by dividing twr (in ns) by tck (in ns) and rounding up to the next inte ger: wrmin[cycles] = roundup(twr[ns]/tck[ ns]). the wr must be programmed to be equal to or larger than twr(min).
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 12 rev. 00a 04/16/2012 2.3.2.6 precharge pd dll mr0 (bit a12) is used to select the dll usage during precha rge power-down mode. when mr0 (a12 = 0), or ?slow-exit?, the dll is frozen after entering precharge power-down (for potential power savings) and upon exit requires txpdll to be met prior to the next valid command. when mr0 (a12 = 1), or ?fast-exit?, the dll is maintained after entering precharge power-down and upon exiting power-down requires t xp to be met prior to the next valid command. 2.3.3 mode register mr1 the mode register mr1 stores the data for enabling or disa bling the dll, output driver strength, rtt_nom impedance, additive latency, write leveling enable, tdqs enable and qoff. the mode register 1 is writte n by asserting low on cs#, ras#, cas#, we#, high on ba0 and low on ba1 and ba2, while controlling the states of address pins according to figure 2.3.3. * 1 : a8, a10, and a13 must be programmed to 0 during mrs. * tdqs must be disabled for x16 option. figure 2.3.3 mr1 definition 2.3.3.1 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon returning to normal operation after having the dll disabled. during no rmal operation (dll-on) with mr1 (a0 = 0), the dll is automatically disabled when entering self -refresh operation and is automatically re-enabled upon exit of self-refresh operation. any time the dll is enabled and subsequently re set, tdllk clock cycles must occur before a read or synchronous odt command can be issued to allow time for the in ternal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the tdqsck, taon or taof parameters. during tdllk, cke must continuously be register ed high. ddr3 sdram does not require dll for any write operation, except ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 0 10* 1 qof f tdqs 0* 1 rtt 0* 1 level rtt d.i.c al rtt d.i.c dll mode register 1 a11 tdqs enable a7 write leveling enable a9 a6 a2 rtt_nom *3 a0 dll enable 0 disabled 0 disabled 0 0 0 odt disabled 0 enable 1 enabled 1 enabled 001 rzq/4 1 disable 010 rzq/2 a4 a3 additive latency 011 rzq/6 0 0 0 (al disabled) 100 rzq/12 *4 01 cl-1 101 rzq/8 *4 10 cl-2 110 reserved 11 reserved 1 1 1 reserved n ote: rzq = 240 ? 01 mr1 10 mr2 a5 a1 output driver impedance control 11 mr3 0 0 rzq/6 0 1 rzq/7 1 0 rzq/tbd 1 1 rzq/tbd
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 13 rev. 00a 04/16/2012 when rtt_wr is enabled and the dll is required for pr oper odt operation. for more detailed information on dll disable operation refer to ?dll-off mode?. the direct odt feature is not supported during dll-off m ode. the on-die termination re sistors must be disabled by continuously registering the odt pin low and/or by programmi ng the rtt_nom bits mr1{a9,a6,a2} to {0,0,0} via a mode register set command during dll-off mode. the dynamic odt feature is not supported at dll-off mode. user must use mrs command to set rtt_wr, mr2 {a10, a9} = {0,0}, to disable dynamic odt externally. 2.3.3.2 output driver impedance control the output driver impedance of the ddr3 sdram device is se lected by mr1 (bits a1 and a5) as shown in figure 2.3.3. 2.3.3.3 odt rtt values ddr3 sdram is capable of providing two different terminat ion values (rtt_nom and rtt_wr). the nominal termination value rtt_nom is programmed in mr1. a separate value (rtt_wr) may be programmed in mr2 to enable a unique rtt value when odt is enabled during writes. the rtt_wr val ue can be applied during writes even when rtt_nom is disabled. 2.3.3.4 additive latency (al) additive latency (al) operation is supported to make co mmand and data bus efficient for sustainable bandwidths in ddr3 sdram. in this operation, the ddr3 sdram allows a read or write command (either with or without auto- precharge) to be issued immediately after the active command. the command is held for the time of the additive latency (al) before it is issued inside the devic e. the read latency (rl) is controlled by the sum of the al and cas latency (cl) register settings. write latency (wl) is controlled by the su m of the al and cas write latency (cwl) register settings. a summary of the al register options are shown in table below. a4 a3 additive latency (al) settings 0 0 0 (al disabled) 0 1 cl - 1 1 0 cl - 2 1 1 reserved note: al has a value of cl - 1 or cl - 2 as per the cl values programmed in the mr0 register . 2.3.3.5 write leveling for better signal integrity, ddr3 memory module adopted fl y-by topology for the commands, addresses, control signals, and clocks. the fly-by topology has the benefit of reducing the nu mber of stubs and their length, but it also causes flight time skew between clock and strobe at every dram on the dimm. this makes it difficult for the controller to maintain tdqss, tdss, and tdsh specification. t herefore, the ddr3 sdram supports a ?w rite leveling? feature to allow the controller to compensate for skew. 2.3.3.6 output disable the ddr3 sdram outputs may be enabled/disabled by mr1 (bit a12) as shown in figure 2. 3.3. when this feature is enabled (a12 = 1), all output pins (dqs, dqs, dqs#, etc.) ar e disconnected from the device, thus removing any loading of the output drivers. this feature ma y be useful when measuring module power, for example. for normal operation, a12 should be set to ?0?. 2.3.3.7 tdqs, tdqs# tdqs (termination data strobe) is a feature of x8 ddr3 sd ram that provides additional termination resistance outputs that may be useful in some system configurations. the td qs function is available in x8 ddr3 sdram only and must be disabled via the mode register a11=0 in mr1 for x16 configuration.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 14 rev. 00a 04/16/2012 2.3.4 mode register mr2 the mode register mr2 stores the data for controlling re fresh related features, rtt_wr impedance, and cas write latency. the mode register 2 is written by asserting lo w on cs#, ras#, cas#, we#, high on ba1 and low on ba0 and ba2, while controlling the states of address pins according to the below. * 1 : a5, a8, a11 ~ a13 must be programmed to 0 during mrs. * 2 : the rtt_wr value can be applied during writes even when rtt_ nom is disabled. during write le veling, dynamic odt is not av ailable . figure 2.3.4 mr2 definition 2.3.4.1 partial array self-refresh (pasr) if pasr (partial array self-refresh) is enabled, data located in areas of the array beyond the specif ied address range shown in figure 2.3.4 will be lost if self-refresh is entered. data integrity will be maintain ed if trefi conditions are met and no self-refresh command is issued. 2.3.4.2 cas write latency (cwl) the cas write latency is defined by mr2 (bits a3-a5), as show n in figure 2.3.4. cas write lat ency is the delay, in clock cycles, between the internal write command and the availabilit y of the first bit of input data. ddr3 sdram does not support any half-clock latencies. the overall write latency (w l) is defined as additive latency (al) + cas write latency (cwl); wl = al + cwl. for more information on the s upported cwl and al settings based on the operating clock frequency, refer to ?standard speed bins?. 2.3.4.3 auto self-refresh (asr) and self-refresh temperature (srt) for more details refer to ? extended temperature usage ?. ddr3 sdrams support self-ref resh operation at all supported temperatures. applications requiring self-refresh opera tion in the extended temperature range must use the asr function or program the srt bit appropriately. ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 0 0* 1 rtt_wr 0* 1 srt asr cwl pasr mode register 2 a7 self-refresh temperature (srt) range a2 a1 a0 partial array self-refresh (optional) 0 n ormal operating temperature range 0 00 full array 1 extended operating temperature range 0 01 halfarray (ba[2:0]=000,001,010, &011) 0 10 quarter array (ba[2:0]=000, & 001) 0 11 1/8th array (ba[2:0] = 000) a6 auto self-refresh (asr) 1 00 3/4 array (ba[2:0] = 010,011,100,101,110, & 111) 0 manual sr reference (srt) 1 01 halfarray (ba[2:0] = 100, 101, 110, &111) 1 asr enable 1 10 quarter array (ba[2:0]=110, &111) 1 11 1/8th array (ba[2:0]=111) a10 a9 rtt_wr *2 a5 a4 a3 cas write latency (cwl) 0 0 dynamic odt off (write does not affect rtt value) 0 00 5 (tck(avg) ? 2.5 ns) 0 1rzq/4 0 01 6 (2.5 ns > tck(avg) ? 1.875 ns) 1 0rzq/2 0 10 7 (1.875 ns > tck(avg) ? 1.5 ns) 1 1 reserved 0 11 8 (1.5 ns > tck(avg) ? 1.25 ns) 1 00 9 (1.25 ns > tck(avg) ? 1.07ns) ba1 ba0 mr select 1 01 10 (1.07 ns > tck(avg) ? 0.935 ns) 0 0mr0 1 10 11 (0.935 ns > tck(avg) ? 0.833 ns) 0 1mr1 1 11 12 (0.833 ns > tck(avg) ? 0.75 ns) 1 0mr2 1 1mr3
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 15 rev. 00a 04/16/2012 2.3.4.4 dynamic odt (rtt_wr) ddr3 sdram introduces a new feature ?dynamic odt?. in certain application cases and to further enhance signal integrity on the data bus, it is desira ble that the termination strength of t he ddr3 sdram can be changed without issuing an mrs command. mr2 register locations a9 and a10 config ure the dynamic odt setings. in write leveling mode, only rtt_nom is available. for details on dynamic odt operation, refer to ?dynamic odt?. 2.3.5 mode register mr3 the mode register mr3 controls multi-purpose registers. t he mode register 3 is written by asserting low on cs#, ras#, cas#, we#, high on ba1 and ba0, and low on ba2 while controlli ng the states of address pins according to the below. * 1 : a3 - a13 must be programmed to 0 during mrs. * 2 : the predefined pattern will be used for read synchronization. * 3 : when mpr control is set for normal operation (mr3 a[2] = 0) then mr3 a[1:0] will be ignored . figure 2.3.5 mr3 definition 2.3.5.1 multi-purpose register (mpr) the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2=1. prior to issuing the mrs command, all banks must be in the idle state (all bank s precharged and trp met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. when the mpr is enabled, only rd or rda commands are allowed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2=0). power down mode, self-refresh and any other non-rd/rd a command is not allowed during mpr enable mode. the reset function is support ed during mpr enable mode. the multi purpose register (mpr) function is used to read out a predefined system timing calibration bit sequence. the basic concept of the mpr is shown in figure 2.3.5.1. ba2 ba1 ba0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 11 0* 1 mp r mpr loc mode register 3 mrp operation mpr address a2 mp r a1 a0 mpr location 0 n ormal operation *3 00 predefined pattern *2 1 dataflow from mp r 01 rfu 10 rfu 11 rfu ba1 ba0 mr select 0 0mr0 0 1mr1 1 0mr2 1 1mr3
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 16 rev. 00a 04/16/2012 figure 2.3.5.1 mpr block diagram to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2 = 1. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp met). once the mpr is enabled, any subsequent rd or rda commands will be redirected to the multi purpose register. the resulting operation, when a rd or rda command is issued, is defined by mr3 bits a[1:0] when the mpr is enabled. when the mpr is enabled, only rd or rda commands are allo wed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2 = 0). note that in mpr mode rda has the same functionality as a read command which means the auto precharge part of rda is ignored. power-down mode, self-refresh and any other non-rd/rda command is not allowed during mpr enable mode. the reset function is supported during mpr enable mode. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function mpr mpr-loc 0b don?t care (0b or 1b) normal operation, no mpr transaction. all subsequent reads will come from dram array. all subsequent writ e will go to dram array. 1b see table 13 enable mpr mode, subsequent rd/rda commands defined by mr3 a[1:0]. memory core (all banks precharged) multipurpose register pre-defined data for read mr3[a2] dq, dm, dqs, dqs#
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 17 rev. 00a 04/16/2012 mpr register address definition the following table provides an overview of the available dat a locations, how they are addr essed by mr3 a[1:0] during a mrs to mr3, and how their individual bits are mapped into the burst order bits during a multi purpose register read. mpr mr3 register definition mr3 a[2] mr3 a[1:0] function burst length read address a[2:0] burst order and data pattern 1b 00b read predefined pattern for system calibration bl8 000b burst order 0,1,2,3,4,5,6,7 pre-defined data pattern [0,1,0,1,0,1,0,1] bc4 000b burst order 0,1,2,3 pre-defined data pattern [0,1,0,1] bc4 100b burst order 4,5,6,7 pre-defined data pattern [0,1,0,1] 1b 01b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 1b 10b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 1b 11b rfu bl8 000b burst order 0,1,2,3,4,5,6,7 bc4 000b burst order 0,1,2,3 bc4 100b burst order 4,5,6,7 note: burst order bit 0 is assigned to lsb and the burst order bit 7 is assigned to msb of the selected mpr agent mpr functional description ? one bit wide logical interface via all dq pins during read operation. ? register read on x16: o dql[0] and dqu[0] drive information from mpr. o dql[7:1] and dqu[7:1] either drive the same information as dql[0], or they drive 0b. ? addressing during for multi purpose register reads for all mpr agents: o ba[2:0]: don?t care o a[1:0]: a[1:0] must be equal to ?00?b. data read burst order in nibble is fixed o a[2]: for bl=8, a[2] must be equal to 0b, burst orde r is fixed to [0,1,2,3,4,5 ,6,7], *) for burst chop 4 cases, the burst order is switched on nibble base a[2] =0b, burst order: 0,1,2,3 *) a[2]=1b, burst order: 4,5,6,7 *) o a[9:3]: don?t care o a10/ap: don?t care o a12/bc: selects burst chop mode on-the-fly, if enabled within mr0. o a11, a13: don?t care ? regular interface functionality during register reads: o support two burst ordering which are switched with a2 and a[1:0]=00b. o support of read burst chop (m rs and on-the-fly via a12/bc) o all other address bits (remaining column address bits including a10, all bank address bits) will be ignored by the ddr3 sdram. o regular read latencies and ac timings apply. o dll must be locked prior to mpr reads. note: *) burst order bit 0 is assigned to lsb and burst order bit 7 is assigned to msb of the selected mpr agent. note: good reference for the example of mpr feature is the jedec standard no.93-3d, 4.10.4 protocol example.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 18 rev. 00a 04/16/2012 relevant timing parameters ac timing parameters are important for operating the multi purpose register: tr p, tmrd, tmod, and tmprr. for more details refer to ?electrical characteristics & ac timing?
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 19 rev. 00a 04/16/2012 2.4 ddr3 sdram command description and operation 2.4.1 command truth table [ba=bank address, ra=row address, ca=column address, bc#=burst chop , x=don?t care, v=valid] function abbrevia tion cke cs# ras # cas # we # ba 0-2 a11, a13 a12/ bc# a10/ ap a0- a9 notes previous cycle current cycle mode register set mrs h h l l l l b a op code refresh ref h h l l l h v v v v v self refresh entry sre h l l l l h v v v v v 7,9,12 self refresh exit srx l h h x x x x x x x x 7,8,9, 12 l h h h v v v v v single bank precharge pre h h l l h l ba v v l v precharge all banks pre a h h l l h l v v v h v bank activate a ct h h l l h h ba row address(ra) write (fixed bl8 or bc4) wr h h l h l l ba rfu v l ca write (bc4, on the fly) wrs4 h h l h l l ba rfu l l ca write (bl8, on the fly) wrs8 h h l h l l ba rfu h l ca write with auto precharge (fixed bl8 or bc4) wr a h h l h l l ba rfu v h ca write with auto precharge (bc4, on the fly) wras4 h h l h l l ba rfu l h ca write with auto precharge (bl8, on the fly) wras8 h h l h l l ba rfu h h ca read (fixed bl8 or bc4) rd h h l h l h ba rfu v l ca read (bc4, on the fly) rds4 h h l h l h ba rfu l l ca read (bl8, on the fly) rds8 h h l h l h ba rfu h l ca read with auto precharge (fixed bl8 or bc4) rd a h h l h l h ba rfu v h ca read with auto precharge (bc4, on the fly) rdas4 h h l h l h ba rfu l h ca read with auto precharge (bl8, on the fly) rdas8 h h l h l h ba rfu h h ca no operation nop h h l h h h v v v v v 10 device deselected des h h h x x x x x x x x 11 power down entry pde h l l h h h v v v v v 6,12 h x x x x x x x x power down exit pdx l h l h h h v v v v v 6,12 h x x x x x x x x zq calibration long zqcl h h l h h l x x x h x zq calibration short zqcs h h l h h l x x x l x notes: 1. all ddr3 sdram commands are defined by states of cs#, ras#, cas#, we# and cke at the rising edge of the clock. the msb of ba , ra and ca are device density and configuration dependant. 2. reset# is low enable command which will be used only for asynch ronous reset so must be maintained high during any function. 3. bank addresses (ba) determine which bank is to be operat ed upon. for (e)mrs ba selects an (extended) mode register. 4. ?v? means ?h or l (but a defined logic level)? and ?x? means either ?defined or undefined (like floating) logic level?. 5. burst reads or writes cannot be terminated or in terrupted and fixed/on-the-fly bl will be defined by mrs. 6. the power down mode does not perform any refresh operation. 7. the state of odt does not affect the states described in this table. the odt function is not available during self refresh. 8. self refresh exit is asynchronous. 9. vref(both vrefdq and vrefca) must be maintained during self refresh operation. vrefdq supply may be turned off and vrefdq ma y take any value between vss and vdd during self refresh operation, provided that vrefdq is valid and stable prior to cke going back high and that first write operation or first write leveling activity may not occur earlier than 512 nck after exit from self refresh. 10. the no operation command should be used in cases when the ddr3 s dram is in an idle or wait state. the purpose of the no ope ration command (nop) is to prevent the ddr3 sdram from registering any unwanted commands between operations. a no operation command will not t erminate a pervious operation that is still executing, such as a burst read or write cycle. 11. the deselect command performs the same function as no operation command. 12. refer to the cke truth table for more detail with cke transition.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 20 rev. 00a 04/16/2012 2.4.1. cke truth table current state 2 cke command (n) 3 ras#, cas#, we#, cs# action (n) 3 notes previous cycle 1 (n-1) current cycle 1 (n) power-down l l x maintain power-down 14,15 l h deselect or nop power-down exit 11,14 self-refresh l l x maintain self-refresh 15,16 l h deselect or nop self-refresh exit 8,12,16 bank(s) active h l deselect or no p active power-down entry 11,13,14 reading h l deselect or nop power-down entry 11,13,14,17 writing h l deselect or nop power-down entry 11,13,14,17 precharging h l deselect or no p power-down entry 11,13,14,17 refreshing h l deselect or nop pr echarge power-down entry 11 all bank idle h l deselect or nop pr echarge power-down entry 11,13,14,18 h l refresh self-refresh 9.13.18 notes: 1. cke (n) is the logic state of cke at clock edge n; c ke (n-1) was the state of cke at the previous clock edge. 2. current state is defined as the state of t he ddr3 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and acti on (n) is a result of command (n), odt is not included here. 4. all states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. the state of odt does not affect the states described in this table. the odt function is not available during self-refresh. 6. cke must be registered with the same value on tckemin consec utive positive clock edges. cke must remain at the valid input l evel the entire time it takes to achieve the tckemin clocks of registeration. thus, afte r any cke transition, cke may not transition from its valid lev el during the time period of tis + tckemin + tih. 7. deselect and nop are defined in the command truth table. 8. on self-refresh exit deselect or nop commands must be i ssued on every clock edge occurring during the txs period. read or od t commands may be issued only after txsdll is satisfied. 9. self-refresh mode can only be entered from the all banks idle state. 10. must be a legal command as defined in the command truth table. 11. valid commands for power-down entry and exit are nop and deselect only. 12. valid commands for self-refresh exit are nop and deselect only. 13. self-refresh cannot be entered during read or write operations. 14. the power-down does not perform any refresh operations. 15. ?x? means ?don?t care? (incl uding floating around vref) in self-refresh and power-down. it also applies to address pins. 16. vref (both vref_dq and vref_ca) must be maintained during self-refresh operation.vrefdq supply may be turned off and vrefdq may take any value between vss and vdd during self refresh operation, provi ded that vrefdq is valid and stable prior to cke going back h igh and that first write operation or first write leveling activity may not occur earlier than 512 nck after exit from self refresh. 17. if all banks are closed at the conclusion of the read, write or precharge command, then precharge power-down is entered, ot herwise active power- down is entered. 18. ?idle state? is defined as all banks are closed (trp, tdal, et c. satisfied), no data bursts are in progress, cke is high, a nd all timings from previous operations are satisfied (tmrd, tmod, trfc, tzqinit, tzqoper, tzqc s, etc.) as well as all self-refresh exit and power-down exit parameters are satisfied (txs, txp, txpdll, etc). 2.4.2 no operation (nop) command the no operation (nop) command is used to instruct t he selected ddr3 sdram to perform a nop ( cs# low and ras#,cas#,we# high). this prevents unwanted commands from bei ng registered during idle or wait states. operations already in progress are not affected. 2.4.3 deselect(des) command the deselect function (cs# high) pr events new commands from being execut ed by the ddr3 sdram. the ddr3 sdram is effectively deselected. operations already in progress are not affected.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 21 rev. 00a 04/16/2012 2.4.4 dll-off mode ddr3 dll-off mode is entered by setting mr1 bit a0 to ?1?; th is will disable the dll for subsequent operations until a0 bit set back to ?0?. the mr1 a0 bit for dll control can be switch ed either during initialization or later. the dll-off mode operations listed below are an optional feature for ddr3. the maximum clock frequency for dll-off mode is specified by the parameter tckdll_off. there is no minimum frequency limit besides the need to satisfy the refresh interval, trefi. due to latency counter and timing restrictions, only one val ue of cas latency (cl) in mr0 and cas write latency (cwl) in mr2 are supported. the dll-off mode is only required to support setting of both cl=6 and cwl=6. dll-off mode will affect the read data clock to data strobe relationship (tdqsc k) but not the data strobe to data relationship (tdqsq, tqh). special attention is needed to line up read data to controller time domain. comparing with dll-on mode, where tdqsck starts from the rising clock edge (al+cl) cycles after the read command, the dll-off mode tdqsck starts (al+cl-1) cycles after t he read command. another difference is that tdqsck may not be small compared to tck (it might even be larger than tck) and the difference between tdqsckmin and tdqsckmax is significantly larger than in dll-on mode. the timing rela tions on dll-off mode read operation have shown at the following timing diagram (cl=6, bl=8) note: the tdqsck is used here for dqs, dqs, and dq to have a simplified diagram; the dll_off shift will affect both timings in the same way and the skew between all dq, dqs, and dqs# signals will still be tdqsq . figure 2.4.4 dll-off mode read timing operation ck# ck command address dqs,dqs#(dll_on) dq(dll_on) dqs,dqs#(dll_off) dq(dll_off) dqs,dqs#(dll_off) dq(dll_off) tdqsck(dll_off)_min tdqsck(dll_off)_max rl (dll_off) = al+(cl-1) = 5 rl (dll_on) = al+cl =6 (cl=6,al=0) cl=6 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 read nop nop nop nop nop nop nop nop nop nop don?t care
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 22 rev. 00a 04/16/2012 2.4.5 dll on/off switching procedure ddr3 dll-off mode is entered by setting mr1 bit a0 to ?1?; th is will disable the dll for subsequent operation until a0 bit set back to ?0?. 2.4.5.1 dll ?on? to dll ?off? procedure to switch from dll ?on? to dll ?off? requires te frequency to be changed duri ng self-refresh outlined in the following procedure: 1. starting from idle state (all banks pre-charged, all timi ng fulfilled, and drams on-die termination resistors, rtt, must be in high impedance state before mrs to mr1 to disable the dll). 2. set mr1 bit a0 to ?1? to disable the dll. 3. wait tmod. 4. enter self refresh mode; wa it until (tcksre) satisfied. 5. change frequency, in guidance with ?i nput clock frequency change? section. 6. wait until a stable clock is available for at least (tcksrx) at dram inputs. 7. starting with the self refresh exit command, cke must c ontinuously be registered high until all tmod timings from any mrs command are satisfied. in addition, if any odt f eatures were enabled in the mode registers when self refresh mode was entered, the odt signal must continuousl y be registered low until all tmod timings from any mrs command are satisfied. if both odt features were disabl ed in the mode registers when self refresh mode was entered, odt signal can be registered low or high. 8. wait txs, and then set mode regist ers with appropriate values (especially an update of cl, cwl, and wr may be necessary. a zqcl command may also be issued after txs). 9. wait for tmod, and then dram is ready for next command. 2.4.5.2 dll ?off? to dll ?on? procedure to switch from dll ?off? to dll ?on? (with required frequency change) during self-refresh: 1. starting from idle state (all banks pre-charged, all timi ngs fulfilled and drams on-die termination resistors (rtt) must be in high impedance state befor e self-refresh mode is entered.) 2. enter self refresh mode, wait until tcksre satisfied. 3. change frequency, in guidance wi th "input clock frequency change". 4. wait until a stable clock is available for at least (tcksrx) at dram inputs. 5. starting with the self refresh exit command, cke must continuously be registered high until tdllk timing from subsequent dll reset command is satisfied. in addition, if any odt features were enabled in the mode registers when self refresh mode was entered, the odt signal must continuously be registered low until tdllk timings from subsequent dll reset command is satisfied. if both odt f eatures are disabled in the mode registers when self refresh mode was entered, odt signal can be registered low or high. 6. wait txs, then set mr1 bit a0 to ?0? to enable the dll. 7. wait tmrd, then set mr0 bit a8 to ?1? to start dll reset. 8. wait tmrd, then set mode registers with appropriate values (especially an update of cl, cwl and wr may be necessary. after tmod satisfied from any proceeding mrs command, a zqcl command may also be issued during or after tdllk.) 9. wait for tmod, then dram is ready for next command (remember to wait tdllk after dll reset before applying command requiring a locked dll!). in addition, wait also for tzqoper in case a zqcl command was issued.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 23 rev. 00a 04/16/2012 2.4.6. input clock frequency change once the ddr3 sdram is initialized, the ddr3 sdram requires the clock to be ?s table? during almost all states of normal operation. this means that, once the clock frequency has been set and is to be in the stable state?, the clock period is not allowed to deviate except for what is allow ed for by the clock jitter and ssc (spread spectrum clocking) specifications. the input clock frequency can be changed from one stable cloc k rate to another stable clock rate under two conditions: (1) self-refresh mode and (2) precharge power-down mode. outs ide of these two modes, it is illegal to change the clock frequency. for the first condition, once the ddr3 sdram has been successfully placed in to self-refresh mode and tcksre has been satisfied, the state of the cloc k becomes a don?t care. once a don?t care, changing the clock frequency is permissible, provided the new clock frequency is stable prio r to tcksrx. when entering and exiting self-refresh mode for the sole purpose of changing the clock frequency, the self -refresh entry and exit specifications must still be met. the ddr3 sdram input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. any frequen cy change below the minimum operating frequency would require the use of dll_on- mode -> dll_off -mode transit ion sequence, refer to ?dll on/off switching procedure?. the second condition is when the ddr3 sdram is in precharge power-down mode (either fast exit mode or slow exit mode). if the rtt_nom feature was enabled in the mode regi ster prior to entering precharge power down mode, the odt signal must continuously be registered low ensuring rtt is in an off state. if the rtt_nom feature was disabled in the mode register prior to entering precharge power down mode, rtt will remain in the off state. the odt signal can be registered either low or high in this case. a minimum of tcksre must occur after cke goes low before the clock frequency may change. the ddr3 sdram input clock frequen cy is allowed to change only within the minimum and maximum operating frequency specified for the particula r speed grade. during the input clock frequency change, odt and cke must be held at stable low levels. once the input clock frequency is changed, stable new clocks must be provided to the dram tcksrx before precharge power-down may be exited; after prechar ge power-down is exited and txp has expired, the dll must be reset via mrs. dep ending on the new clock freque ncy, additional mrs commands may need to be issued to appropriately set the wr, cl, and cw l with cke continuously registered high. during dll re- lock period, odt must remain low and cke must remain high. after the dll lock time, the dram is ready to operate with new clock frequency. 2.4.7 write leveling for better signal integrity, the ddr3 memory module adopt ed fly-by topology for the commands, addresses, control signals, and clocks. the fly-by topology has benefits from reducing number of stubs and their length, but it also causes flight time skew between clock and strobe at every dram on the dimm. this make s it difficult for the controller to maintain tdqss, tdss, and tdsh specification. therefore, the ddr3 sdra m supports a ?write leveling? feature to allow the controller to compensate for skew. the memory controller can use the ?write leveling? feat ure and feedback from the ddr3 sdram to adjust the dqs - dqs# to ck - ck# relationship. the memory controller involved in the leveling must have adjustable delay setting on dqs - dqs# to align the rising edge of dqs - dqs# with that of the clock at the dram pin. the dram asynchronously feeds back ck - ck#, sampled with the rising edge of dq s - dqs#, through the dq bus. the controller repeatedly delays dqs - dqs# until a transition from 0 to 1 is detected. the dqs - dqs# delay established though this exercise would ensure tdqss specification. besides tdqss, tdss and tdsh specification also needs to be fu lfilled. one way to achieve this is to combine the actual tdqss in the application with an appropriate duty cycle and jitte r on the dqs - dqs# signals. depending on the actual tdqss in the application, the actual values for tdqsl and tdqsh may have to be better than the absolute limits provided in the chapter "ac timing parameters" in order to satisf y tdss and tdsh specification. a conceptual timing of this scheme is shown in figure 2.4.7.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 24 rev. 00a 04/16/2012 figure 2.4.7 write leveling concept dqs - dqs# driven by the controller during leveling mode must be terminated by the dram based on ranks populated. similarly, the dq bus driven by the dram mu st also be terminated at the controller. one or more data bits should carry the leveling feedback to the controller across the dram configurations x8 and x16. on a x16 device, both byte lanes should be leveled independently. therefore, a separate feedback mechanism should be avail able for each byte lane. the upp er data bits should provide the feedback of the upper diff_dqs(diff_udqs) to clock relation ship whereas the lower data bits would indicate the lower diff_dqs(diff_ldqs) to clock relationship. 2.4.7.1 dram setting for write leveling & dram termination function in that mode dram enters into write leveling mode if a7 in mr1 set ?high? and after finishing leveling, dram exits from write leveling mode if a7 in mr1 set ?low?. note that in write leveling m ode, only dqs/dqs# terminations are activated and deactivated via odt pin, unlike normal operation. mr setting involved in the leveling procedure function mr1 enable disable write leveling enable a7 1 0 output buffer mode (qoff) a12 0 1 dram termination function in the leveling mode odt pin @dram dqs/dqs# termination dqs termination de-asserted off off asserted on off note: in write leveling mode with its output buffer disabled (mr1[b it7] = 1 with mr1[bit12] = 1) all rtt_nom settings are allow ed; in write leveling mode with its output buffer enabled (mr1[bit7] = 1 with mr1[bit12] = 0) only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are all owed. ck# ck diff_dqs source destination ck# ck diff_dqs dq diff_dqs dq push dqs to capture 0-1 transition 0 or 1 0 0 0 0 or 1 111 t0 t1 t2 t3 t4 t5 t6 t7 t0 t1 t2 t3 t4 t5 t6 tn
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 25 rev. 00a 04/16/2012 2.4.7.2 procedure description the memory controller initiates leveling mode of all drams by setting bit 7 of mr1 to 1. when entering write leveling mode, the dq pins are in undefined driving mode. during write leveling mode, only no p or deselect commands are allowed, as well as an mrs command to exit write leveling m ode. since the controller levels one rank at a time, the output of other ranks must be disabled by setting mr1 bit a12 to 1. the controller may assert odt after tmod, at which time the dram is ready to accept the odt signal. the controller may drive dqs low and dqs# high after a del ay of twldqsen, at which time the dram has applied on- die termination on these signals. after tdqsl and twlmrd, the controller provides a single dqs, dqs# edge which is used by the dram to sample ck - ck# driven from c ontroller. twlmrd(max) timing is controller dependent. dram samples ck - ck# status with rising edge of dq s - dqs# and provides feedback on all the dq bits asynchronously after twlo timing. either one or all data bi ts ("prime dq bit(s)") provide the leveling feedback. the dram's remaining dq bits are driven low statically after the fi rst sampling procedure. there is a dq output uncertainty of twloe defined to allow mismatch on dq bits. the twloe period is defined from the transition of the earliest dq bit to the corresponding transition of the latest dq bit. there are no read strobes (dqs/dqs#) need ed for these dqs. controller samples incoming dq and decides to increment or decrement dqs - dqs# delay setting and launches the next dqs/dqs# pulse after some time, which is controller dependent. once a 0 to 1 transition is detected, the controller locks dqs - dqs# delay setting and write leveling is achieved for the device. figure 2.4.7.2 describes the timing diagram and parameters for the overall write leveling procedure. notes: 1. dram has the option to drive leveling feedback on a prime dq or all dqs. if feedback is driven only on one dq, the remainin g dqs must be driven low, as shown in above figure, and maintained at this state throughout the leveling procedure. 2. mrs: load mr1 to enter write leveling mode. 3. nop: nop or deselect. 4. diff_dqs is the differential data strobe (dqs, dqs#). timing re ference points are the zero crossings. dqs is shown with soli d line, dqs# is shown with dotted line. 5. ck, ck# : ck is shown with solid dark li ne, where as ck# is drawn with dotted line. 6. dqs, dqs# needs to fulfill minimum pulse width requirements tdqsh(min) and tdqsl(min) as def ined for regular writes; the max pulse width is system dependent. figure 2.4.7.2 write leveling sequence [dqs - dqs# is capturing ck-ck# low at t1 and ck-ck# high at t2] ck# (5) ck cmd mrs nop nop tmod nop nop nop t1 twlh twls t2 twlh twls nop nop nop nop nop nop don?t care undefined drivin g mode time break odt diff_dqs (4) one prime dq: prime dq (1) late remaining dqs early remaining dqs late remaining dqs (1) early remaining dqs (1) all dqs are prime: (2) (3) twldqsen tdqsl (6) tdqsh (6) tdqsl (6) tdqsh (6) twlmrd twlmrd twlo twlo twlo twlo twloe twlo twlo twlo twlo twloe
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 26 rev. 00a 04/16/2012 2.4.7.3 write leveling mode exit the following sequence describes how the write leveling mode should be exited: 1. after the last rising strobe edge, stop driving the strobe signals. note: from now on, dq pins are in undefined driving mode, and will remain undefined, until tmod after the respective mr command. 2. drive odt pin low (tis must be sati sfied) and continue registering low. 3. after the rtt is switched off, dis able write level mode via mrs command. 4. after tmod is satisfied, any valid command may be registered. (mr commands may be issued after tmrd ). 2.4.8 extended temperature usage a. auto self-refresh supported b. extended temperature range supported c. double refresh required for operation in the extended temperature range (applies only for devices supporting the extended temperature range) mode register description field bits description auto sel f -refresh (asr) when enabled, ddr3 sdram automatically provides self-refresh power management functions for all supported operating temperature values. if not enabled, the srt bit must be programmed to indicate toper asr mr2 (a6) during subsequent self-refresh operation 0 = manual sr reference (srt) 1 = asr enable sel f -refresh temperature (srt) range if asr = 0, the srt bit must be programmed to indicate toper during subsequent self-refresh operation srt mr2 (a7) if asr = 1, srt bit must be set to 0b 0 = normal operating temperature range 1 = extended operating temperature range 2.4.8 1 auto self-refresh mode - asr mode ddr3 sdram provides an auto self-refresh mode (asr ) for application ease. asr mode is enabled by setting mr2 bit a6 = 1b and mr2 bit a7 = 0b. the dram will manage self-ref resh entry in either the normal or extended (optional) temperature ranges. in this mode, the dram will also manage self-refresh power consumption when the dram operating temperature changes, lower at low te mperatures and higher at high temperatures. if the asr option is not supported by the dram, mr2 bit a6 must be set to 0b. if the asr mode is not enabled (mr2 bit.a6 = 0b), the srt bit (mr2 a7) must be manually programmed with the operating temperature range required during self-refresh operation. support of the asr option does not automatically imply support of the extended temperature range.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 27 rev. 00a 04/16/2012 4.9.1 self-refresh temperature range - srt srt applies to devices supporting extended temperature range only. if asr = 0b, the self-refresh temperature (srt) range bit must be programmed to guarant ee proper self-refresh operation. if srt = 0b, then the dram will set an appropriate refresh rate for self-refre sh operation in the normal temperatur e range. if srt = 1b then the dram will set an appropriate, potentially different, refresh rate to allow self-refresh operation in either the normal or extended temperature ranges. the value of the srt bit can effect self -refresh power consumption, please refer to the idd table for details. for parts that do not support the extended temperature rang e, mr2 bit a7 must be set to 0b and the dram should not be operated outside the normal temperature range. self-refresh mode summary mr2 a[6] mr2 a[7] self-refresh operation allowed operating temperature range for self-refresh mode 0 0 self-refresh rate appropriate for the normal temperature range normal (0 - 85 o c) 0 1 self-refresh rate appropriate for either the normal or extended temperature ranges. the dram must support extended temperature range. the value of the srt bit can effect self- refresh power consumption, pleas e refer to the idd table for details. normal and extended (0 - 95 o c) 1 0 asr enabled (for devices supporting asr and normal temperature range). self-ref resh power consumption is temperature dependent normal (0 - 85 o c) 1 0 asr enabled (for devices supporting asr and extended temperature range). self-ref resh power consumption is temperature dependent normal and extended (0 - 95 o c) 1 1 illegal
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 28 rev. 00a 04/16/2012 3. absolute maximum ratings and ac & dc operating conditions 3.1 absolute maximum dc ratings. symbol parameter rating units note vdd voltage on vdd pin relative to vss -0.4 v ~ 1.975 v v 1,3 vddq voltage on vddq pin relative to vss -0.4 v ~ 1.975 v v 1,3 vin, vout voltage on any pin relative to vss -0.4 v ~ 1.975 v v 1 tstg storage temperature -55 to +100 c 1,2 notes: 1. stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the opera tional sections of this s pecification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on t he center/top side of the dram. for the measurement conditions. 3. vdd and vddq must be within 300 mv of each other at all times; and vref must be not greater than 0.6 x vddq, when vdd and vddq are less than 500 mv; vref may be equal to or less than 300 mv 3.2 component operating temperature range symbol parameter rating units notes toper for commercial normal operating temperature range 0 to 85 c 1,2 extended temperature range 85 to 95 c 1,3 toper for industrial and automotive normal operating temperature range -40 to 0 c 1 toper for automotive (a2 only) normal operating temperature range 95 to 105 c 1,3 notes: 1. operating temperature toper is the case surface temperature on the center / top side of the dram. 2. the normal temperature range specifie s the temperatures where all dram specific ations will be supported. during operation, t he dram case temperature must be maintained between 0 to 85 c under all operating conditions 3. some applications require operation of the dram in the extended temperature range above 85 c case temperature. full specifications are supported in this range, but the fo llowing additional conditions apply: a ) refresh commands must be doubled in frequency, theref ore reducing the refresh interval trefi to 3.9 s. b) if self-refresh operation is required in the extended temperatur e range, then it is mandatory to either use the manual self- refresh mode with extended temperature range capability (mr2 a6 = 0b and mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b). 3.3 recommended dc operating conditions(sstl_1.5) symbol parameter rating unit notes min typ max vdd supply voltage 1.425 1.5 1.575 v 1,2 vddq supply voltage for ou tput 1.425 1.5 1.575 v 1,2 notes: 1. under all conditions vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd and vddq tied together.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 29 rev. 00a 04/16/2012 4. ac & dc input measurement levels 4.1. ac and dc logic input levels for single-ended signals 4.1.1 ac and dc input levels for si ngle-ended command and address signals symbol parameter ddr3-800/1066/1333/1600 unit note min max vih.dq(dc100) dc input logic high vref + 0.100 vdd v 1 vil.dq(dc100) dc input logic low vss vref - 0.100 v 1 vih.dq(ac175) ac input logic high vref + 0.175 note 2 v 1,2 vil.dq(ac175) ac input logic low note 2 vref - 0.175 v 1,2 vih.ca(ac150) ac input logic high vref + 0.150 note2 v 1,2 vil.ca(ac150) ac input logic low note2 vref - 0.150 v 1,2 vrefca(dc) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd v 3,4 notes: 1. for input only pins except reset.vref=vrefca(dc) 2. see "overshoot and undershoot specifications" 3. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than +/- 0.1% vdd. 4. for reference: approx. vdd/2 +/- 15mv. 5. to allow vrefca margining, all dram command and address input buffers must use external vref (provided by system) as the inp ut for their vrefca pins. all vih/l input level must be compared with the ex ternal vref level at the 1st stage of the command and address in put buffer 4.1.2 ac and dc logic input levels for single-ended signals & dq and dm symbol parameter ddr3-800/1066 ddr3-1333/1600 unit note min. max. min. max. vih.dq(dc100) dc input logic high vref +0.100 vdd vref +0.100 vdd v 1 vil.dq(dc100) dc input logic low vss vref -0.100 vss vref -0.100 v 1 vih.dq(ac175) ac input logic high vref +0 .175 note2 vref +0.150 note2 v 1,2,5 vil.dq(ac175) ac input logic low note2 vr ef -0.175 note2 vref -0.150 v 1,2,5 vih.dq(ac150) ac input logic high vref +0 .150 note2 vref +0.150 note2 v 1,2,5 vil.dq(ac150) ac input logic low note2 vr ef -0.150 note2 vref -0.150 v 1,2,5 vrefdq(dc) reference voltage for dq, dm inputs 0.49 *vdd 0.51 *vdd 0.49 *vdd 0.51 *vdd v 3,4 vrefdq_t(dc) reference voltage for trained dq, dm inputs 0.45 *vdd 0.55 *vdd 0. 45 *vdd 0.55 *vdd v 3,4, 6,7 notes: 1. for input only pins except reset#. vref = vrefdq(dc) 2. see "overshoot and undershoot specifications" 3. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than 0.1% vdd. 4. for reference: approx. vdd/2 15mv. 5. single-ended swing requirement for dqs-dqs#, is 350mv (peak to peak). differential swing requirement for dqs-dqs#, is 700mv (peak to peak) 6. vrefdq training is performed only during system boot. once th e training is completed and an optimal vrefdq_t(dc) voltage lev el is identified, the optimal vrefdq_t(dc) voltage level will be used during system runtim e. during vrefdq training, vrefdq is swept from 40% of vdd to 60% of vdd to find the optimal vrefdq_t(dc) voltage level; and once the optimal vref dq_t(dc) is set, it must stay within 1% of its set value as well as not be less than 45% of vdd or exceed 55% of vdd. vih.dq(ac)min/vil.dq(ac)ma x = optimal vrefdq_t(dc) ac lev el, where "ac level" is the act ual ac voltage level per ddr3 speed bins as specifi ed in jesd79-3 specification. after vrefdq training is completed and the optimal vr efdq_t(dc) is set, the memory controller provides the dram device a valid write window. through dqs placement optimization and vrefdq centering, the v alid write window is optimized for both input voltage margin and tds+tdh window for the dram receiver. the dram device supports the use of the ab ove techniques to optimize the write timing and voltage margin, as long as the tec hnique does not create any dimm failures due to dram input volt age and/or timing spec violations as defined in jesd79-3 specification. 7. to allow vrefdq margining, all dram data input buffers must use external vref (provided by system) as the input for their vr efdq pins. all vih/l input level must be compared with the external vref level at the 1st stage of the data input buffer .
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 30 rev. 00a 04/16/2012 4.2 vref tolerances the dc-tolerance limits and ac-moist limit s for the reference voltages vrefca and vr efdq are illustrated in the following figure. it shows a valid reference voltage vref(t) as a func tion of time. (vref stands for vrefca and vrefdq likewise). vref(dc) is the linear average of vref(t) ov er a very long period of time (e.g.,1 sec). this average has to meet the min/max requirement in previous page. furthermore vref(t) may tem porarily deviate from vref(dc) by no more than 1% vdd. the voltage levels for setup and hold time measurements vi h(ac), vih(dc), vil(ac), and vil(dc) are dependent on vref. ?vref? shall be understood as vref(dc) . the clarifies that dc-variations of vr ef affect the absolute voltage a signal has to reach to achieve a valid high or low level and theref ore the time to which setup and hold is measured. system timing and voltage budgets need to account for vref(dc) deviations from the optimum position within the data-eye of the input signals. this also clarifies that the dram setup/hold specific ation and de-rating values need to include time and voltage associated with vref ac-noise. timing and voltage effects due to ac-noise on vref up to the specified limit (1% of vdd) are included in dram timing and their associated de-ratings. figure 4.2 illustration of vref(dc) tolerance and vrefac-noise limits volta g e vref ( d vref ac-noise vref ( t ) vref ( dc ) vref ( dc ) vdd vss time
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 31 rev. 00a 04/16/2012 4.3. ac and dc logic input leve ls for differential signals 4.3.1 differential signal definition figure 4.3.1 definition of differential ac-swing and ?time above ac-level? 4.3.2 differential swing requirements for cl ock (ck - ck#) and strobe (dqs - dqs#) 4.3.2.1 differential ac and dc input levels symbol parameter ddr3-800, 1066, 1333, & 1600 unit notes min max vihdiff differential input logic high +0.200 note3 v 1 vildiff differential input logic low note3 -0.200 v 1 vihdiff(ac) differential input high ac 2 x ( vih(ac) ? vref ) note3 v 2 vildiff(ac) differential input low ac note3 2 x ( vref - vil(ac) ) v 2 notes: 1. used to define a differential signal slew-rate. 2. for ck - ck# use vih/vil(ac) of add/cmd and vrefca; for dqs - dqs#, dqsl, dqsl#, dqsu, dqsu# use vih/vil(ac) of dqs and vref dq; if a reduced ac-high or ac-low level is used for a si gnal group, then the reduced level applies also here. 3. these values are not defined; however, t he single-ended signals ck, ck#, dqs, dqs#, dq sl, dqsl#, dqsu, dqsu# need to be within the respective limits (vih(dc) max, vil(dc)min) for single-ended signals as well as the limitat ions for overshoot and undershoot . 4.3.2.2 allowed time before ringback (tdvac) for ck - ck# and dqs - dqs# slew rate [v/ns] tdvac [ps] @ivih/ldiff(ac)i = 350mv tdvac [ps] @ivih/ldiff(ac)i = 300mv min max min max > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 - tdvac v ih.diff.ac.min v ih.diff.min v ih.diff.max v ih.diff.ac.max half c y cle tdvac time differential input voltage (i.e. dqs?dqs#, ck?ck#)
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 32 rev. 00a 04/16/2012 4.3.3. single-ended requirements for differential signals each individual component of a differential signal (ck, dqs, dqsl, dqsu, ck#, dqs#, dqsl#, or dqsu#) has also to comply with certain requirem ents for single-ended signals. ck and ck# have to approximately reach vsehmin / vselmax (appr oximately equal to the ac-levels (vih(ac) / vil(ac) ) for add/cmd signals) in every half-cycle. dqs, dqsl , dqsu, dqs#, dqsl# have to reach vsehmin / vselmax (approximately the ac-levels (vih(ac) / vil(ac) ) for dq signals) in every half-cycle preceding and following a valid transition. 4.3.3.1. single-ended levels for ck, dqs, dqsl, dqsu, ck#, dq s#, dqsl# or dqsu# symbol parameter ddr3-800, 1066, 1333, & 1600 unit notes min max vseh single-ended high-level for strobes (vddq/2) + 0.175 note3 v 1, 2 single-ended high-level for ck, ck (vddq/2) + 0.175 note3 v 1, 2 vsel single-ended low-level for strobes note3 (vddq/2) - 0.175 v 1, 2 single-ended low-level for ck, ck note3 (vddq/2) - 0.175 v 1, 2 notes: 1. for ck, ck# use vih/vil(ac) of add/cm d; for strobes (dqs, dqs#, dqsl, dqsl#, dqsu, dqsu#) use vih/vil(ac) of dqs. 2. vih(ac)/vil(ac) for dqs is based on vrefdq; vih(ac)/vil(ac) fo r add/cmd is based on vrefca; if a reduced ac-high or ac-low l evel is used for a signal group, then the reduced level applies also here 3. these values are not defined, however the single-ended signals ck, ck#, dqs, dqs#, dqsl , dqsl#, dqsu, dqsu# need to be within t he respective limits (vih(dc) max, vil(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. figure 4.3.3 single-ended requirement for differential signals. vss or vssq vselmax vdd/2 or vddq/2 vsehmin vsel vseh ck or dqs time vdd or vddq
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 33 rev. 00a 04/16/2012 4.4 differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (ck, ck and dqs, dqs) must meet the requirements in the following table. the differential input cross point voltage vix is measured from the actual cross point of true and completement signal to the midlevel between of vdd and vss. figure 4.4. vix definition 4.4.1 cross point voltage for differ ential input signals (ck, dqs) symbol parameter ddr3-800, 1066, 1333, & 1600 unit note min. max. vix differential input cross point vo ltage relative to vdd/2 for ck, ck -150 150 mv -175 175 mv 1 differential input cross point vo ltage relative to vdd/2 for dqs, dqs -150 150 mv note: 1. extended range for vix is only allowed for clock and if singl e-ended clock input signals ck and ck# are monotonic with a sin gle-ended swing vsel / vseh of at least vdd/2 +/-250 mv, and when the different ial slew rate of ck - ck# is larger than 3 v/ns. 4.5 slew rate definitions for single-ended input signals see ?address / command setup, hold and derating? for single-ended slew rate definitions for address and command signals. see ?data setup, hold and slew rate derating? for single-ended slew rate definitions for data signals. vdd ck#,dqs# vdd/2 ck,dqs vss v ix v ix v ix
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 34 rev. 00a 04/16/2012 4.6. slew rate definition fo r differential input signals 4.6.1 differential input slew rate definition description measured defined by from to differential input slew rate for rising edge (ck-ck# & dqs- dqs#) vildiffmax vihdiffmin [vihdiffm in-vildiffmax] / deltatrdiff differential input slew rate for falling edge (ck-ck# & dqs- dqs#) vihdiffmin vildiffmax [vihdiffm in-vildiffmax] / deltatfdiff note : the differential signal (i.e., ck-ck# & dq s-dqs#) must be linear between these thresholds. figure 4.6.1 input nominal slew rate definition for dqs, dqs# and ck, ck# differential input voltage(i.e. dqs - dqs#, ck - ck#)
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 35 rev. 00a 04/16/2012 5. ac and dc output measurement levels 5.1 single ended ac and dc output levels symbol parameter value unit notes voh(dc) dc output high measurement level (f or iv curve linearity) 0.8xvddq v vom(dc) dc output mid measurement level (f or iv curve linearity) 0.5xvddq v vol(dc) dc output low measurement level (f ro iv curve linearity) 0.2xvddq v voh(ac) ac output high measurement leve l (for output sr) vtt+0.1xvddq v 1 vol(ac) ac output low measurement leve l (for output sr) vtt-0.1xvddq v 1 note 1. the swing of 0.1 vddq is based on approximately 50% of the static single-ended output high or low swing with a driv er impedance of 40 ? and an effective test load of 25 ? to vtt = vddq/2. 5.2 differential ac and dc output levels symbol parameter value unit notes vohdiff(ac) ac differential output high measurem ent level (for output sr) +0.2 x vddq v 1 voldiff(ac) ac differential output low measurem ent level (for output sr) -0.2 x vddq v 1 note 1. the swing of 0.2 vddq is based on approximately 50% of the static single-ended output high or low swing with a driv er impedance of 40 ? and an effective test load of 25 ? to vtt = vddq/2 at each of the differential outputs. 5.3 single ended output slew rate 5.3.1 single ended output slew rate definition description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) [voh(ac)-vol(ac)] / deltatrse single ended output slew rate for falling edge voh(ac) vol(ac) [voh(ac)-vol(ac)] / deltatfse figure 5.3.1 single ended output slew rate definition 5.3.2 output slew rate (single-ended) parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit min. max. min. max. max. max. max. max. single-ended output slew rate sr qse 2.5 5 2.5 5 2.5 5 tbd 5 v/ns note: sr: slew rate. q: query output (like in dq, which stands for data-in, query -output). se: single-ended signals. for ron = rzq/7 setting. single ended output voltage(i.e. dq)
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 36 rev. 00a 04/16/2012 5.4 differential output slew rate 5.4.1 differential output slew rate definition description measured defined by from to differential output slew rate for rising voldiff(ac) vohdiff(ac) [vohdiff(ac )-voldiff(ac)]/deltatrdiff differential output slew rate for falling vohdiff(ac) voldiff(ac) [v ohdiff(ac)-voldiff(ac)]/deltatfdiff note: output slew rate is verified by design and characterization, and not 100% tested in production . figure 5.4.1 differential output slew rate definition 5.4.2 differential output slew rate parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit min. max. min. max. max. max. max. max. differential output slew rate srqdiff 5 10 5 10 5 10 tbd 10 v/ns description: sr: slew rate, q: query output (like in dq, which stands for data-in, query-out put), diff: differential signals, f or ron = rzq/7 setting 5.5 reference load for ac timing and output slew rate the following figure represents the effective reference load of 25 ohms used in defining the relevant ac timing parameters of the device as well as output slew rate measurements. it is not intended as a precise representation of any particular system environment or a depiction of the actual load present ed by a production tester. system designers should use ibis or other simulation tools to correlate the timing reference lo ad to a system environment. manuf acturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. figure 5.5 reference load for ac timing and output slew rate ck,ck# dut dq, dqs, dqs# vddq 25ohm vtt=vddq/2 timing reference point
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 37 rev. 00a 04/16/2012 5.6 overshoot and undershoot specifications 5.6.1 ac overshoot/undershoot specification for address and control pins item ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed fo r undershoot area 0.4 0.4 0.4 0.4 v maximum overshoot area above vdd 0.67 0.5 0.4 0.33 v-ns undershoot area below vss 0.67 0.5 0.4 0.33 v-ns note : a0-a13, ba0-ba2, cs#, ras#, cas#, we#, cke, odt 5.6.2 ac overshoot/undershoot specification for clock, data, strobe, and mask item ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units maximum peak amplitude allowed for overshoot area 0.4 0.4 0.4 0.4 v maximum peak amplitude allowed fo r undershoot area 0.4 0.4 0.4 0.4 v maximum overshoot area above vd d 0.25 0.19 0.15 0.13 v-ns undershoot area below vss 0.25 0.19 0.15 0.13 v-ns note : ck, ck#, dq, dqs, dqs#, dm 5.7 34ohm output driver dc electrical characteristics a functional representation of the output buffer is shown as below. output driver impedance ron is defined by the value ofthe external reference resistor rzq as follows: ron34 = rzq / 7 (nominal 34.4ohms +/-10% with nominal rzq=240ohms) the individual pull-up and pull-down resistors (ronpu and ronpd) are defined as follows: ronpu = [vddq-vout] / | iout | ------------------- under the condition that ronpd is turned off (1) ronpd = vout / | iout | ---------------------------- ---under the condition that ronpu is turned off (2) maximum amplitude overshoot area undershoot area maximum amplitude vdd vss volts(v) time(ns) maximum amplitude vddq vssq volts(v) time(ns) maximum amplitude overshoot area
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 38 rev. 00a 04/16/2012 figure 5.7 output driver : definition of voltages and currents 5.7.1 output driver dc electrical characteristics (assuming rzq = 240ohms; entire operating temperature range; after proper zq calibration) ronnom resistor vout min nom max unit notes 34 ohms ron34pd voldc=0.2xvddq 0.6 1 1.1 rzq/7 1,2,3 vomdc=0.5xvddq 0.9 1 1.1 rzq/7 1,2,3 vohdc =0.8xvddq 0.9 1 1.4 rzq/7 1,2,3 ron34pu voldc=0.2xvddq 0.9 1 1.4 rzq/7 1,2,3 vomdc=0.5xvddq 0.9 1 1.1 rzq/7 1,2,3 vohdc=0.8xvddq 0.6 1 1.1 rzq/7 1,2,3 mismatch between pull-up and pull-down, mmpup d vomdc= 0.5xvddq -10 +10 % 1,2,4 notes: 1. the tolerance limits are specified after calibration with st able voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following se ction on voltage and temperature sensitivity. 2. the tolerance limits are specified under the condition that vddq=vdd and that vssq=vss. 3. pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5xvddq. other calibration schemes may b e used to achieve the linearity spec shown above, e.g. calibration at 0.2 * vddq and 0.8 x vddq. 4. measurement definition for mismatch between pull-up and pull-down, mmpupd: measure ronpu and ronpd, both at 0.5 x vddq: mmpupd = [ronpu - ronpd] / ronnom x 100 5.7.2 output driver temperature and voltage sensitivity if temperature and/or voltage after calibration, the tole rance limits widen according to the following table below. delta t = t - t(@calibration); delta v = vddq - vddq(@calibration); vdd = vddq 5.7.2.1 output driver sensitivity definition items min. max. unit ronpu@vohdc 0.6 - drondth*ldelta tl - drondvh*ldelta vl 1.1 + drondth*ldelta tl - drondvh*ldelta vl rzq/7 ron@vomdc 0.9 - drondtm*ldelta tl - drondvm*ldelta vl 1.1 + drondtm*ldelta tl - drondvm*ldelta vl rzq/7 ronpd@voldc 0.6 - drondtl*ldelta tl - drondvl*ldelta vl 1.1 + drondtl*ldelta tl - drondvl*ldelta vl rzq/7 note: drondt and drondv are not subject to producti on test but are verified by design and characterization. vddq dq vssq to other circuitry ronpu ronpd i pu i pd output driver chip in drive mode iout vout
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 39 rev. 00a 04/16/2012 5.7.2.2 output driver voltage and temperature sensitivity speed bin ddr3-800/1066/1333 ddr3-1600 unit items min. max min. max drondtm 0 1.5 0 1.5 %/c drondvm 0 0.15 0 0.13 %/mv drondtl 0 1.5 0 1.5 %/c drondvl 0 0.15 0 0.13 %/mv drondth 0 1.5 0 1.5 %/c drondvh 0 0.15 0 0.13 %/mv note: drondt and drondv are not subject to producti on test but are verified by design and characterization. 5.8 on-die termination (odt) levels and i-v characteristics 5.8.1 on-die termination (odt) levels and i-v characteristics on-die termination effective resistance rtt is def ined by bits a9, a6, and a2 of the mr1 register. odt is applied to the dq, dm, dqs/dqs, and tdqs/tdqs (x8 devices only) pins. a functional representation of the on-die termination is show n in the following figure. the individual pull-up and pull-down resistors (rttpu and rttpd) are defined as follows: rttpu = [vddq - vout] / | iout | ------------------ under the condition that rttpd is turned off (3) rttpd = vout / | iout | ------------------------------ under the condition that rttpu is turned off (4) figure 5.8.1 on-die termination : definition of voltages and currents 5.8.2 odt dc electrical characteristics the following table provides an overview of the odt dc el ectrical characteristics. the values for rtt60pd120, rtt60pu120, rtt120pd240, rtt120pu240, rtt40pd80, rtt40pu80, rtt30pd60, rtt30pu60, rtt20pd40, rtt20pu40 are not specification requirement s, but can be used as design guide lines: vddq dq vssq to other circuitry rttpu rttpd i pu i pd odt chip in termination mode iout vout iout = ipd -ipu
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 40 rev. 00a 04/16/2012 odt dc electrical characteristics (assuming rzq = 240ohms +/- 1% entire operating te mperature range; after proper zq calibration) mr1 a9, a6, a2 rtt resistor vout min nom max unit notes 0,1,0 120 ? rtt120pd240 voldc = 0.2 x vddq 0. 6 1 1.1 rzq 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq 1,2,3,4 vohdc = 0.8 x vddq 0. 9 1 1.4 rzq 1,2,3,4 rtt120pu240 voldc = 0.2 x vddq 0. 6 1 1.1 rzq 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq 1,2,3,4 vohdc = 0.8 x vddq 0. 9 1 1.4 rzq 1,2,3,4 rtt120 vil(ac) to vih(ac ) 0.9 1 1.6 rzq/2 1,2,5 0,0,1 60 ? rtt60pd120 voldc = 0.2 x vddq 0. 6 1 1.1 rzq/2 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/2 1,2,3,4 vohdc = 0.8 x vddq 0. 9 1 1.4 rzq/2 1,2,3,4 rtt 60pu120 voldc = 0.2 x vddq 0. 6 1 1.1 rzq/2 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/2 1,2,3,4 vohdc = 0.8 x vddq 0. 9 1 1.4 rzq/2 1,2,3,4 rtt60 vil(ac) to vih(ac) 0.9 1 1.6 rzq/4 1,2,5 0,1,1 40 ? rtt40pd80 voldc = 0.2 x vddq 0. 6 1 1.1 rzq/3 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/3 1,2,3,4 vohdc = 0.8 x vddq 0. 9 1 1.4 rzq/3 1,2,3,4 rtt40pu80 voldc = 0.2 x vddq 0. 6 1 1.1 rzq/3 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/3 1,2,3,4 vohdc = 0.8 x vddq 0. 9 1 1.4 rzq/3 1,2,3,4 rtt40 vil(ac) to vih(ac) 0.9 1 1.6 rzq/6 1,2,5 1,0,1 30 ? rtt30pd60 voldc = 0.2 x vddq 0. 6 1 1.1 rzq/4 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/4 1,2,3,4 vohdc = 0.8 x vddq 0. 9 1 1.4 rzq/4 1,2,3,4 rtt30pu60 voldc = 0.2 x vddq 0. 6 1 1.1 rzq/4 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/4 1,2,3,4 vohdc = 0.8 x vddq 0. 9 1 1.4 rzq/4 1,2,3,4 rtt30 vil(ac) to vih(ac) 0.9 1 1.6 rzq/8 1,2,5 1,0,0 20 ? rtt20pd40 voldc = 0.2 x vddq 0. 6 1 1.1 rzq/6 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/6 1,2,3,4 vohdc = 0.8 x vddq 0. 9 1 1.4 rzq/6 1,2,3,4 rtt20pu40 voldc = 0.2 x vddq 0. 6 1 1.1 rzq/6 1,2,3,4 0.5 x vddq 0.9 1 1.1 rzq/6 1,2,3,4 vohdc = 0.8 x vddq 0. 9 1 1.4 rzq/6 1,2,3,4 rtt20 vil(ac) to vih(ac ) 0.9 1 1.6 rzq/12 1,2,5 notes: 1. the tolerance limits are specified after calibration with st able voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibration, see following se ction on voltage and temperature sensitivity. 2. the tolerance limits are specified under the co ndition that vddq = vdd and that vssq = vss. 3. pull-down and pull-up odt resistors are recommended to be calibrated at 0.5 x vddq. other calibration schemes may be used to achieve the linearity spec shown above. 4. not a specification requireme nt, but a design guide line. 5. measurement definition for rtt: apply vih(ac) to pin under test and measure current i(vih(ac)), then apply vil(ac) to pin under test and measure current i(vil( ac)) respectively. rtt = [vih(ac) - vil(ac)] / [i(vih(ac)) - i(vil(ac))] 6. measurement definition for vm and dvm: measure voltage (vm) at test pin (midpoint) with no load: delta v m = [2v m / vddq -1] x 100
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 41 rev. 00a 04/16/2012 5.8.3 odt temperature and voltage sensitivity if temperature and/or voltage after calibration, the to lerance limits widen according to the following table. delta t = t - t(@calibration); delta v = vddq - vddq(@calibration); vdd = vddq 5.8.3.1 odt sensitivity definition min max unit rtt 0.9 - drttdt*ldelta tl - drttdv*ldelta vl 1.6 + drttdt*ldelta tl + drttdv*ldelta vl rzq/2,4,6,8,12 5.8.3.2 odt voltage and temperature sensitivity min max unit drttdt 0 1.5 %/c drttdv 0 0.15 %/mv note: these parameters may not be subject to producti on test. they are verified by design and characterization 5.9 odt timing definitions 5.9.1 test load for odt timings different than for timing measurements, the reference l oad for odt timings is defined in the following figure. figure 5.9.1 odt timing reference load 5.9.2 odt timing definitions definitions for t aon , t aonpd , t aof , t aofpd , and t adc are provided in the following table and subsequent figures. symbol begin point definition end point definition t aon rising edge of ck - ck defined by the en d point of odtlon extrapolated point at vssq t aonpd rising edge of ck - ck with odt being firs t registered high extr apolated point at vssq t aof rising edge of ck - ck defined by the end poin t of odtloff end point: extrapolated point at v rtt_nom t aofpd rising edge of ck - ck with odt being first r egistered low end point: extrapolated point at v rtt_nom t adc rising edge of ck - ck defined by the end point of odtlcnw, odtlcwn4, or odtlcwn8 end point: extrapolated point at v rtt_wr and v rtt _ nom respectively reference settings for odt timing measurements measured parameter rtt_nom settin g rtt_wr setting vsw1[v] vsw2[v] t aon rzq/4 na 0.05 0.10 rzq/12 na 0.10 0.20 t aonpd rzq/4 na 0.05 0.10 rzq/12 na 0.10 0.20 t aofpd rzq/4 na 0.05 0.10 rzq/12 na 0.10 0.20 t adc rzq/12 rzq/2 0.20 0.30 ck,ck# dut dq,dm dqs, dqs#, tdqs, tdqs# 25ohm vtt=vssq timing reference point vddq vssq
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 42 rev. 00a 04/16/2012 figure 5.9.2.1 definition of t aon figure 5.9.2.2 definition of t aonpd begin point : rising edge of ck-ck# with odt being first register high end point : extrapolated point at vssq ck ck# vtt vsw2 dq,dm,dqs, dqs#,tdqs, tdqs# vssq t aonpd vsw1 tsw1 tsw2 begin point : rising edge of ck-ck# defined by the end of odtlon end point : extrapolated point at vssq ck ck# vtt vsw2 dq,dm,dqs, dqs#,tdqs, tdqs# vssq t aon vsw1 tsw1 tsw2
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 43 rev. 00a 04/16/2012 figure 5.9.2.3 definition of t aof figure 5.9.2.4 definition of t aofpd begin point : rising edge of ck-ck# with defined by the end point of odtloff end point : extrapolated point at v rtt_nom ck ck# vtt vsw2 dq,dm,dqs, dqs#,tdqs, tdqs# vssq t aof vsw1 tsw1 tsw2 v rtt nom begin point : rising edge of ck-ck# with odt being first registered low end point : extrapolated point at v rtt_nom ck ck# vtt vsw2 dq,dm,dqs, dqs#,tdqs, tdqs# vssq t aofpd vsw1 tsw1 tsw2 v rtt nom
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 44 rev. 00a 04/16/2012 figure 5.9.2.5 definition of t adc begin point : rising edge of ck-ck# defined by the end point of odtlcnw begin point : rising edge of ck-ck# defined by the end point of odtlcwn4 or odtlcwn8 t adc t adc end point : extrapolated point at v rtt_wr end point : extrapolated point at v rtt_nom dq,dm,dqs, dqs#,tdqs, tdqs# ck ck# vtt vssq v rtt_nom tsw11 tsw21 tsw22 tsw12 vsw2 vsw1 v rtt_wr
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 45 rev. 00a 04/16/2012 6. input / output capacitance symbol parameter ddr3-800 ddr3- 1066 ddr3- 1333 ddr3- 1600 units notes min max min max min max min max c io input/output capacitance (dq, dm, dqs,dqs#,tdqs,tds#) 1.5 3 1.5 3 1.5 2.5 1.5 2.3 pf 1,2,3 c ck input capacitance, ck and ck# 0.8 1.6 0.8 1.6 0.8 1. 4 0.8 1.4 pf 2,3 c dck input capacitance delta, ck and ck # 0 0.2 0 0.2 0 0. 2 0 0.2 pf 2,3,4 c ddqs input/output capacitance delta, dqs and dqs# 0 0.2 0 0.2 0 0.2 0 0.2 pf 2,3,5 c i input capacitance, ctrl, add, command input-only pins 0.8 1.4 0.8 1.4 0.8 1. 3 0.8 1.3 pf 2,3,7,8 c di_ctrl input capacitance delta, all ctrl input- only pins -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 pf 2,3,7,8 c di_add_cm d input capacitance delta, all add/cmd input-only pins -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 pf 2,3,9,1 0 c dio input/output capacitance delta, dq, dm, dqs, dqs# tdqs,tdqs# tdqs -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pf 2,3,11 c zq input/output capacitance of zq pin - 3 - 3 - 3 - 3 pf 2,3,12 notes: 1. although the dm, tdqs and tdqs# pins have diffe rent functions, the l oading matches dq and dqs 2. this parameter is not subject to pr oduction test. it is verified by design and characterization. vdd=vddq=1.5v, vbias=vdd/2 and on-die termination off. 3. this parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. absolute value of c ck -c ck # 5. absolute value of c io (dqs)-c io (dqs#) 6. c i applies to odt, cs#, cke, a0-a13, ba0-ba2, ras#,cas#,we#. 7. c di_ctrl applies to odt, cs# and cke 8. c di_ctrl =c i (ctrl)-0.5*(c i (ck)+c i (ck#)) 9. c di_add_cmd applies to a0-a13, ba0-ba2, ras#, cas# and we# 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (ck)+c i (ck#)) 11. c dio =c io (dq,dm) - 0.5*(c io (dqs)+c io (dqs#)) 12. maximum external load c apacitance on zq pin: 5 pf.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 46 rev. 00a 04/16/2012 7. idd specifications and measurement conditions idd specifications (x8), 1.5 operation voltage symbol parameter/condition operation voltage ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 unit typ. max. typ. max. typ. max. typ. max. typ. max. typ. idd0 operating current 0 -> one bank activate-> precharge 1.5v 50 56 53 59 58 65 tbd tbd tbd tbd ma idd1 operating current 1 -> one bank activate-> read-> precharge 1.5v 67 74 71 79 76 83 tbd tbd tbd tbd ma idd2p0 precharge power-down current slow exit - mr0 bit a12 = 0 1.5v 5 9 5 9 5 9 tbd tbd tbd tbd ma idd2p1 precharge power-down current fast exit - mr0 bit a12 = 1 1.5v 16 20 18 22 20 25 tbd tbd tbd tbd ma idd2pq precharge quiet standby current 1.5v 25 31 28 35 31 39 tbd tbd tbd tbd ma idd2n precharge standby current 1.5v 26 32 30 35 33 39 tbd tbd tbd tbd ma idd3p active power-down current always fast exit 1.5v 16 21 19 23 21 26 tbd tbd tbd tbd ma idd3n active standby current 1.5v 29 35 32 38 35 41 tbd tbd tbd tbd ma idd4r operating current burst read 1.5v 97 106 113 122 129 139 tbd tbd tbd tbd ma idd4w operating current burst write 1.5v 94 104 109 119 123 134 tbd tbd tbd tbd ma idd5b burst refresh current 1.5v 47 52 50 55 53 59 tbd tbd tbd tbd ma idd6 self-refresh current normal temperature range (0-85c) 1.5v 3 7 3 7 3 7 tbd tbd tbd tbd ma idd6et self-refresh current: extended temperature range 1.5v 4 8 4 8 4 8 tbd tbd tbd tbd ma idd6tc auto self-refresh current 1.5v 4 8 4 8 4 8 tbd tbd tbd tbd ma idd7 all bank interleave read current 1.5v 169 184 203 220 209 227 tbd tbd tbd tbd ma
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 47 rev. 00a 04/16/2012 idd specifications (x16), 1.5 operation voltage symbol parameter/condition operation voltage ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 unit typ. max. typ. max. typ. max. typ. max. typ. max. typ. idd0 operating current 0 -> one bank activate-> precharge 1.5v 63 76 66 80 73 87 tbd tbd tbd tbd ma idd1 operating current 1 -> one bank activate-> read-> precharge 1.5v 87 106 92 112 98 119 tbd tbd tbd tbd ma idd2p0 precharge power-down current slow exit - mr0 bit a12 = 0 1.5v 5 12 5 13 5 14 tbd tbd tbd tbd ma idd2p1 precharge power-down current fast exit - mr0 bit a12 = 1 1.5v 16 21 18 23 20 26 tbd tbd tbd tbd ma idd2pq precharge quiet standby current 1.5v 26 31 29 34 31 38 tbd tbd tbd tbd ma idd2n precharge standby current 1.5v 27 33 30 35 33 39 tbd tbd tbd tbd ma idd3p active power-down current always fast exit 1.5v 17 25 20 27 22 30 tbd tbd tbd tbd ma idd3n active standby current 1.5v 29 38 33 41 35 45 tbd tbd tbd tbd ma idd4r operating current burst read 1.5v 132 165 157 195 180 224 tbd tbd tbd tbd ma idd4w operating current burst write 1.5v 130 162 152 189 174 216 tbd tbd tbd tbd ma idd5b burst refresh current 1.5v 48 56 51 59 54 62 tbd tbd tbd tbd ma idd6 self-refresh current normal temperature range (0-85c) 1.5v 4 7 4 7 4 7 tbd tbd tbd tbd ma idd6et self-refresh current: extended temperature range 1.5v 4 8 4 8 4 8 tbd tbd tbd tbd ma idd6tc auto self-refresh current 1.5v 4 8 4 8 4 8 tbd tbd tbd tbd ma idd7 all bank interleave read current 1.5v 212 266 236 297 264 332 tbd tbd tbd tbd ma
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 48 rev. 00a 04/16/2012 idd specifications (x8), 1.35 operation voltage symbol parameter/condition operation voltage ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 unit typ. max. typ. max. typ. max. typ. max. typ. max. typ. idd0 operating current 0 -> one bank activate-> precharge 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd1 operating current 1 -> one bank activate-> read-> precharge 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd2p0 precharge power-down current slow exit - mr0 bit a12 = 0 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd2p1 precharge power-down current fast exit - mr0 bit a12 = 1 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd2pq precharge quiet standby current 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd2n precharge standby current 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd3p active power-down current always fast exit 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd3n active standby current 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd4r operating current burst read 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd4w operating current burst write 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd5b burst refresh current 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd6 self-refresh current normal temperature range (0-85c) 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd6et self-refresh current: extended temperature range 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd6tc auto self-refresh current 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma idd7 all bank interleave read current 1.35v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd ma
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 49 rev. 00a 04/16/2012 idd specifications (x16), 1.35 operation voltage symbol parameter/condition operation voltage ddr3-1066 ddr3-1333 ddr3-1600 ddr3-1866 ddr3-2133 unit typ. max. typ. max. typ. max. typ. max. typ. max. typ. idd0 operating current 0 -> one bank activate-> precharge 1.35v 59 69 65 76 69 81 tbd tbd tbd tbd ma idd1 operating current 1 -> one bank activate-> read-> precharge 1.35v 79 93 85 100 90 106 tbd tbd tbd tbd ma idd2p0 precharge power-down current slow exit - mr0 bit a12 = 0 1.35v 3.4 8 3.4 10 3.4 12 tbd tbd tbd tbd ma idd2p1 precharge power-down current fast exit - mr0 bit a12 = 1 1.35v 16 21 18 23 20 26 tbd tbd tbd tbd ma idd2pq precharge quiet standby current 1.35v 25 31 29 34 31 38 tbd tbd tbd tbd ma idd2n precharge standby current 1.35v 26 33 30 35 33 39 tbd tbd tbd tbd ma idd3p active power-down current always fast exit 1.35v 17 25 20 27 22 30 tbd tbd tbd tbd ma idd3n active standby current 1.35v 28 38 32 40 35 45 tbd tbd tbd tbd ma idd4r operating current burst read 1.35v 111 133 132 158 152 182 tbd tbd tbd tbd ma idd4w operating current burst write 1.35v 119 129 141 154 161 176 tbd tbd tbd tbd ma idd5b burst refresh current 1.35v 45 51 49 56 52 60 tbd tbd tbd tbd ma idd6 self-refresh current normal temperature range (0-85c) 1.35v 2 7 2 7 2 7 tbd tbd tbd tbd ma idd6et self-refresh current: extended temperature range 1.35v 2 8 2 8 2 8 tbd tbd tbd tbd ma idd6tc auto self-refresh current 1.35v 2 8 2 8 2 8 tbd tbd tbd tbd ma idd7 all bank interleave read current 1.35v 191 230 222 267 248 298 tbd tbd tbd tbd ma
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 50 rev. 00a 04/16/2012 8. electrical characteristics and ac timing for ddr3-800 to ddr3-1600 8.1 clock specification the jitter specified is a random jitter meeting a gaussian distri bution. input clocks violating the min/max values may result in malfunction of the ddr3 sdram device. 8.1.1 definition for tck(avg) tck(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge. where n=200 8.1.2 definition for tck(abs) tck(abs) is defind as the absolute clock period, as meas ured from one rising edge to the next consecutive rising edge. tck(abs) is not subjec t to production test. 8.1.3 definition for tch(avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses: where n=200 tcl(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses: where n=200 8.1.4 definition for note for tjit(per), tjit(per, ick) tjit(per) is defined as the largest deviation of any single tck from tck(avg). tjit(per) = min/max of {tcki-tck(avg) where i=1 to 200} tjit(per) defines the single period jitter when the dll is already locked. tjit(per,lck) uses the same definition for single period jitter, during the dll locking period only. tjit(per) and tjit(per,lck) are not subject to production test. 8.1.5 definition for tjit (cc), tjit(cc, ick) tjit(cc) is defined as the absolute difference in clock per iod between two consecutive clock cycles: tjit(cc) = max of {tcki+1-tcki} tck(avg) = ( tckj ) / n tch(avg) = ( tchj ) / (n x tck(avg) tcl(avg) = ( tclj ) / (n x tck(avg)
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 51 rev. 00a 04/16/2012 tjit(cc) defines the cycle to cycle jitter when the dll is already locked. tjit(cc,lck) uses the same definition for cycle to cycle jitter, during the dll locking period only. tjit(cc) and tjit(cc,lck) are not subject to production test. 8.1.6 definition for terr(nper) terr is defined as the cumulative error across n multiple consecutive cycles from tck(avg). terr is not subject to production test. 8.2 refresh parameters refresh parameters parameter symbol units all bank refresh to active/refresh cmd time trfc 110 ns average periodic refresh interval trefi -40c < tcase < 85c 7.8 s 85c < tcase < 105c 3.9 s 8.3 speed bins and cl, trcd, trp, trc and tras for corresponding bin ddr3-1066mhz speed bin ddr3-1066 unit cl-nrcd-nrp 7-7-7 (-187f) parameter symbol min max internal read command to first data taa 13.125 20.000 ns act to internal read or write delay time trcd 13.125 - ns pre command period trp 13.125 - ns act to act or ref command period trc 50.625 - ns act to pre command period tras 37.500 9*trefi ns cl=5 cwl =5 tck(avg) 3.000 3.300 ns cwl=6 tck(avg) reserved ns cl=6 cwl =5 tck(avg) 2.500 3.300 ns cwl=6 tck(avg) reserved ns cl=7 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns cl=8 cwl =5 tck(avg) reserved ns cwl=6 tck(avg) 1.875 <2.5 ns supported cl settings 5,6,7,8 nck supported cwl settings 5,6 nck
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 52 rev. 00a 04/16/2012 ddr3-1333mhz speed bin ddr3-1333 unit cl-nrcd-nrp 8-8-8 (-15g) 9-9-9 (-15h) parameter symbol min max min max internal read command to first data taa 12.0 20 13.5 20 ns act to internal read or write delay trcd 12.0 - 13.5 - ns pre command period trp 12.0 - 13.5 - ns act to act or ref period trc 48.0 - 49.5 - ns act to pre command period tras 36.0 9*trefi 36.0 9*trefi ns cl=5 cwl =5 2.500 2.5 3.3 3.0 3.3 ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cl=6 cwl =5 tck(avg) 2.5 3.3 2.5 3.3 ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cl=7 cwl =5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 <2.5 1.875 <2.5 ns cwl=7 tck(avg) reserved reserved ns cl=8 cwl =5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 <2.5 1.875 <2.5 ns cwl=7 tck(avg) 1.5 <1.875 reserved ns cl=9 cwl=5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.5 <1.875 1.5 <1.875 ns cwl=7 tck(avg) reserved reserved ns cl=10 cwl =5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) 1.5 <1.875 1.5 <1.875 ns supported cl settings 5,6,7, 8,9,10 5,6,7, 8,9,10 nck supported cwl settings 5,6,7 5,6,7 nck note : *: optional ddr3-1600mhz speed bin ddr3-1600 unit cl-nrcd-nrp 10-10-10 (-125j) 11-11-11 (-125k) parameter symbol min max min max internal read command to first data taa 12.5 20 13.75 20 ns act to internal read or write delay trcd 12.5 - 13.75 - ns pre command period trp 12.5 - 13.75 - ns act to act or ref period trc 47.5 - 48.75 - ns act to pre command period tras 35 9*trefi 35 9*trefi ns cl=5 cwl =5 tck(avg) 2.5 3.3 3.0 3.3 ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cwl=8 tck(avg) reserved reserved ns cl=6 cwl =5 tck(avg) 2.5 3.3 2.5 3.3 ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cwl=8 tck(avg) reserved reserved ns cl=7 cwl =5 tck(avg) reserved reserved ns
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 53 rev. 00a 04/16/2012 cwl=6 tck(avg) 1.875 <2.5 1.875 <2.5 ns cwl=7 tck(avg) reserved reserved ns cwl=8 tck(avg) reserved reserved ns cl=8 cwl =5 tck(avg) reserved reserved ns cwl=6 tck(avg) 1.875 <2.5 1.875 <2.5 ns cwl=7 tck(avg) reserved reserved ns cwl=8 tck(avg) reserved reserved ns cl=9 cwl =5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) 1.5 <1.875 1.5 <1.875 ns cwl=8 tck(avg) reserved reserved ns cl=10 cwl =5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) 1.5 <1.875 1.5 <1.875 ns cwl =8 tck(avg) 1.25 <1.5 1.25 <1.5 ns cl=11 cwl =5 tck(avg) reserved reserved ns cwl=6 tck(avg) reserved reserved ns cwl=7 tck(avg) reserved reserved ns cwl =8 tck(avg) 1.250* <1.5* 1.250 <1.5 ns supported cl settings 5,6, 8,9,10,11 5,6,7, 8,9,10,11 nck supported cwl settings 5,6,7 5,6,7,8 nck note : *: optional 9. electrical characteristics & ac timing 9.1 timing parameter by speed bin (ddr3-800, ddr3-1066) parameter symbol ddr3-800 ddr3-1066 units notes min. max. min. max. clock timing minimum clock cycle time (dll off mode) tck(dll_off) 8 - 8 - ns 6 average clock period tck(avg) refer to standard speed bins ps average high pulse width tch(avg) 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit(per)min ps max.: tck(avg)max + tjit(per)max absolute clock high pulse width tch(abs) 0.43 - 0.43 - tck(avg) 25 absolute clock low pulse width tcl(abs) 0.43 - 0.43 - tck(avg) 26 clock period jitter jit(per) -100 100 -90 90 ps clock period jitter during dll locking period jit(per, lck) -90 90 -80 80 ps cycle to cycle period jitter tjit(cc) 200 200 180 180 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 180 180 160 160 ps duty cycle jitter tjit(duty) - - - - ps cumulative error across 2 cycles terr(2per) -147 147 -132 132 ps cumulative error across 3 cycles terr(3per) -175 175 -157 157 ps cumulative error across 4 cycles terr(4per) -194 194 -175 175 ps cumulative error across 5 cycles terr(5per) -209 209 -188 188 ps cumulative error across 6 cycles terr(6per) -222 222 -200 200 ps cumulative error across 7 cycles terr(7per) -232 232 -209 209 ps cumulative error across 8 cycles terr(8per) -241 241 -217 217 ps cumulative error across 9 cycles terr(9per) -249 249 -224 224 ps
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 54 rev. 00a 04/16/2012 cumulative error across 10 cycles terr(10per) -257 257 -231 231 ps cumulative error across 11 cycles terr(11per) -263 263 -237 237 ps cumulative error across 12 cycles terr(12per) -269 269 -242 242 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min ps 24 terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max data timing dqs, dqs# to dq skew, per group, per access tdqsq - 200 - 150 ps 13 dq output hold time from dqs, dqs# tqh 0.38 - 0.38 - tck(avg) 13,g dq low-impedance time from ck, ck# tlz(dq) -800 400 -600 300 ps 13,14,f dq high impedance time from ck, ck# thz(dq) - 400 - 300 ps 13,14,f data setup time to dq s, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac175 75 - 25 - ps d,17 data setup time to dq s, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac150 125 - 75 - ps d,17 data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(base) dc100 150 - 100 - ps d,17 dq and dm input pulse width for each input tdipw 600 - 490 - ps 28 data strobe timing dqs,dqs# differential read preamble trpre 0.9 note 19 0.9 note 13,19,g dqs, dqs# differential read postambl e trpst 0.3 note 11 0.3 note 11,13,g dqs, dqs# differential output high time tqsh 0.38 - 0.38 - tck(avg) 13,g dqs, dqs# differential output low time tqsl 0.38 - 0.38 - tck(avg) 13,g dqs, dqs# differential write pream ble twpre 0.9 - 0.9 - tck(avg) dqs, dqs# differential write post amble twpst 0.3 - 0.3 - tck(avg) dqs, dqs# rising edge output access time from rising ck, ck# tdqsck -400 400 -300 300 tck(avg) 13,f dqs and dqs# low-impedance time (referenced from rl - 1) tlz(dqs) -800 400 -600 300 tck(avg) 13,14,f dqs and dqs# high-impedance time (referenced from rl + bl/2) thz(dqs) - 400 - 300 tck(avg) 13,14,f dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 0.45 0.55 tck(avg) 29,31 dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 0.45 0.55 tck(avg) 30,31 dqs, dqs# rising edge to ck, ck# rising edge tdqss -0.25 0.25 -0.25 0.25 tck(avg) c dqs, dqs# falling edge setup time to ck, ck# rising edge tdss 0.2 - 0.2 - tck(avg) c,32 dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.2 - 0.2 - tck(avg) c,32 command and address timing dll locking time tdllk 512 - 512 - nck internal read command to precharge command delay trtp trtpmin.: max(4nck, 7.5ns) e trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) e,18 twtrmax.: write recovery time twr 15 - 15 - ns e,18 mode register set command cycle time tmrd 4 - 4 - nck mode register set command update delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd standard speed bins e pre command period trp standard speed bins e act to act or ref command period trc standard speed bins e cas# to cas# command delay tccd 4 - 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 55 rev. 00a 04/16/2012 multi-purpose register recovery time tmprr 1 - 1 - nck 22 active to precharge command period tras standard speed bins e active to active command period for 1kb page size trrd max(4nck, 10ns) - max(4nck, 7.5ns) - e active to active command period for 2kb page size trrd trrdmin.: max(4nck, 10ns) e trrdmax.: four activate window for 1kb page size tfaw 40 - 37.5 - ns e four activate window for 2kb page size tfaw 50 - 50 - ns e command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) 200 - 125 - ps b,16 command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) 275 - 200 - ps b,16,27 command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac150 200+150 - 125+150 - ps b,16 control and address input pulse width for each input tipw 900 - 780 - ps 28 calibration timing power-up and reset calibration ti me tzqinit 512 - 512 - nck normal operation full calibration time tzqoper 256 - 256 - nck normal operation short calibration time tzqcs 64 - 64 - nck 23 reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a locked dll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) nck 2 txsdllmax.: - minimum cke low width for self refresh entry to exit timing tckesr tckesrmin.: tcke(min) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power-down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power-down exit (pdx) or reset exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max(3nck, 7.5ns) txpmax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck 7.5ns) tckemin.: max(3nck 5.625ns) tckemax.: - tckemax.: - command pass disable delay tcpded tcpdedmin.: 1 nck tcpdedmax.: - power down entry to exit timing tpd tpdmin.: tcke(min) 15 tpdmax.: 9*trefi timing of act command to power down entry tactpden tactpdenmin.: 1 nck 20 tactpdenmax.: - timing of pre or prea command to power down entry tprpden tprpdenmin.: 1 nck 20 tprpdenmax.: - parameter symbol ddr3-800 ddr3-1066 units notes min. max. min. max.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 56 rev. 00a 04/16/2012 timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 nck trdpdenmax.: - timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(avg)) nck 9 twrpdenmax.: - timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 nck 10 twrapdenmax.: - timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) nck 9 twrpdenmax.: - timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 nck 10 twrapdenmax.: - timing of ref command to power down entry trefpden trefpdenmin.: 1 nck 20,21 trefpdenmax.: - timing of mrs command to power down entry tmrspden tmrspdenmin.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 nck odth4max.: - odt high time with write command and bl8 odth8 odth8min.: 6 nck odth8max.: - asynchronous rtt turn-on delay (power- down with dll frozen) taonpd 2 8.5 2 8.5 ns asynchronous rtt turn-off delay (power- down with dll frozen) taofpd 2 8.5 2 8.5 ns rtt turn-on taon -400 400 -300 300 ps 7,f rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 tck(avg) 8,f rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 tck(avg) f write leveling timings first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - 40 - nck 3 dqs/dqs# delay after write leveling mode is programmed twldqsen 25 - 25 - nck 3 write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 325 - 245 - ps write leveling hold time from rising dqs, dqs# crossing to ri sing ck, ck# crossing twlh 325 - 245 - ps write leveling output delay twlo 0 9 0 9 ns write leveling output error twloe 0 2 0 2 ns 9.2 timing parameter by speed bin (ddr3-1333, ddr3-1600) parameter symbol ddr3-1333 ddr3-1600 units notes min. max. min. max. clock timing minimum clock cycle time (dll off mode) tck(dll_off) 8 - 8 - ns 6 average clock period tck(avg) refer to standard speed bins ps average high pulse width tch(avg) 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 tck(avg) absolute clock period tck(abs) min.: tck(avg)min + tjit(per)min ps max.: tck(avg)max + tjit(per)max absolute clock high pulse width tch(abs) 0.43 - 0.43 - tck(avg) 25 absolute clock low pulse width tcl(abs) 0.43 - 0.43 - tck(avg) 26 clock period jitter jit(per) -80 80 -70 70 ps clock period jitter during dll locking period jit(per, lck) -70 70 -60 60 ps cycle to cycle period jitter tjit(cc) 160 160 140 140 ps cycle to cycle period jitter during dll locking period jit(cc, lck) 140 140 120 120 ps
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 57 rev. 00a 04/16/2012 duty cycle jitter tjit(duty) - - - - ps cumulative error across 2 cycles terr(2per) -118 118 -103 103 ps cumulative error across 3 cycles terr(3per) -140 140 -122 122 ps cumulative error across 4 cycles terr(4per) -155 155 -136 136 ps cumulative error across 5 cycles terr(5per) -168 168 -147 147 ps cumulative error across 6 cycles terr(6per) -177 177 -155 155 ps cumulative error across 7 cycles terr(7per) -186 186 -163 163 ps cumulative error across 8 cycles terr(8per) -193 193 -169 169 ps cumulative error across 9 cycles terr(9per) -200 200 -175 175 ps cumulative error across 10 cycles terr(10per) -205 205 -180 180 ps cumulative error across 11 cycles terr(11per) -210 210 -184 184 ps cumulative error across 12 cycles terr(12per) -215 215 -188 188 ps cumulative error across n = 13, 14 . . . 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n)) * tjit(per)min ps terr(nper)max = (1 + 0.68ln(n)) * tjit(per)max data timing dqs, dqs# to dq skew, per group, per access tdqsq - 125 - 100 ps 13 dq output hold time from dqs, dqs# tqh 0.38 - 0.38 - tck(avg) 13,g dq low-impedance time from ck, ck# tlz(dq) -500 250 -450 225 ps 13,14,f dq high impedance time from ck, ck# thz(dq) - 250 - 225 ps 13,14,f data setup time to dq s, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac175 - - - - ps d,17 data setup time to dq s, dqs# referenced to vih(ac) / vil(ac) levels tds(base) ac150 30 - 10 - ps d,17 data hold time from dqs, dqs# referenced to vih(dc) / vil(dc) levels tdh(base) dc100 65 - 45 - ps d,17 dq and dm input pulse width for each input tdipw 400 - 360 - ps 28 data strobe timing dqs,dqs# differential read pr eamble trpre 0.9 note 19 0.9 note 19 note 13,19,g dqs, dqs# differential read po stamble trpst 0.3 note 11 0.3 note 11 note 11,13,g dqs, dqs# differential output high ti me tqsh 0.4 - 0.4 - tck(avg) 13,g dqs, dqs# differential output low ti me tqsl 0.4 - 0.4 - tck(avg) 13,g dqs, dqs# differential write pream ble twpre 0.9 - 0.9 - tck(avg) dqs, dqs# differential write post amble twpst 0.3 - 0.3 - tck(avg) dqs, dqs# rising edge output access time from rising ck, ck# tdqsck -255 255 -225 225 tck(avg) 13,f dqs and dqs# low-impedance time (referenced from rl - 1) tlz(dqs) -500 250 -450 225 tck(avg) 13,14,f dqs and dqs# high-impedance time (referenced from rl + bl/2) thz(dqs) - 250 - 225 tck(avg) 13,14,f dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 0.45 0.55 tck(avg) 29,31 dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 0.45 0.55 tck(avg) 30,31 dqs, dqs# rising edge to ck, ck# rising edge tdqss -0.25 0.25 -0.27 0.27 tck(avg) c dqs, dqs# falling edge setup time to ck, ck# rising edge tdss 0.2 - 0.18 - tck(avg) c,32 dqs, dqs# falling edge hold time from ck, ck# rising edge tdsh 0.2 - 0.18 - tck(avg) c,32 command and address timing dll locking time tdllk 512 - 512 - nck internal read command to precharge command delay trtp trtpmin.: max(4nck, 7.5ns) trtpmax.: - delay from start of internal write transaction to internal read command twtr twtrmin.: max(4nck, 7.5ns) twtrmax.: write recovery time twr 15 - 15 - ns e,18 mode register set command cycle time tmrd 4 - 4 - nck
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 58 rev. 00a 04/16/2012 mode register set command update delay tmod tmodmin.: max(12nck, 15ns) tmodmax.: act to internal read or write delay time trcd standard speed bins pre command period trp standard speed bins act to act or ref command period trc standard speed bins cas# to cas# command delay tccd 4 - 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup(trp / tck(avg)) nck multi-purpose register recovery time tmprr 1 - 1 - nck 22 active to precharge command period tras standard speed bins active to active command period for 1kb page size trrd max(4nck, 6ns) - max(4nck, 6ns) - e active to active command period for 2kb page size trrd trrdmin.: max(4nck, 7.5ns) trrdmax.: four activate window for 1kb page size tfaw 30 - 30 - ns e four activate window for 2kb page size tfaw 45 - 40 - ns e command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) 65 - 45 - ps b,16 command and address hold time from ck, ck# referenced to vih(dc) / vil(dc) levels tih(base) 140 - 120 - ps b,16,27 command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels tis(base) ac150 65+125 - 45+125 - ps b,16 control and address input pulse width for each input tipw 620 - 560 - ps 28 calibration timing power-up and reset calibration ti me tzqinit 512 - 512 - nck normal operation full calibration time tzqoper 256 - 256 - nck normal operation short calibration time tzqcs 64 - 64 - nck 23 reset timing exit reset from cke high to a valid command txpr txprmin.: max(5nck, trfc(min) + 10ns) txprmax.: - self refresh timings exit self refresh to commands not requiring a locked dll txs txsmin.: max(5nck, trfc(min) + 10ns) txsmax.: - exit self refresh to commands requiring a locked dll txsdll txsdllmin.: tdllk(min) nck txsdllmax.: - minimum cke low width for self refresh entry to exit timing tckesr tckesrmin.: tcke(min) + 1 nck tckesrmax.: - valid clock requirement after self refresh entry (sre) or power-down entry (pde) tcksre tcksremin.: max(5 nck, 10 ns) tcksremax.: - valid clock requirement before self refresh exit (srx) or power-down exit (pdx) or reset exit tcksrx tcksrxmin.: max(5 nck, 10 ns) tcksrxmax.: - power down timings exit power down with dll on to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp txpmin.: max(3nck, 6ns) txpmax.: - exit precharge power down with dll frozen to commands requiring a locked dll txpdll txpdllmin.: max(10nck, 24ns) txpdllmax.: - cke minimum pulse width tcke tckemin.: max(3nck 5.625ns) tckemin.: max(3nck 5ns) tckemax.: - tckemax.: - command pass disable delay tcpded tcpdedmin.: 1 nck tcpdedmax.: - power down entry to exit timing tpd tpdmin.: tcke(min) tpdmax.: 9*trefi timing of act command to power down entry tactpden tactpdenmin.: 1 nck tactpdenmax.: -
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 59 rev. 00a 04/16/2012 timing of pre or prea command to power down entry tprpden tprpdenmin.: 1 nck tprpdenmax.: - timing of rd/rda command to power down entry trdpden trdpdenmin.: rl+4+1 nck trdpdenmax.: - timing of wr command to power down entry (bl8otf, bl8mrs, bc4otf) twrpden twrpdenmin.: wl + 4 + (twr / tck(avg)) nck twrpdenmax.: - timing of wra command to power down entry (bl8otf, bl8mrs, bc4otf) twrapden twrapdenmin.: wl+4+wr+1 nck twrapdenmax.: - timing of wr command to power down entry (bc4mrs) twrpden twrpdenmin.: wl + 2 + (twr / tck(avg)) twrpdenmax.: - nck timing of wra command to power down entry (bc4mrs) twrapden twrapdenmin.: wl + 2 +wr + 1 nck twrapdenmax.: - timing of ref command to power down entry trefpden trefpdenmin.: 1 nck trefpdenmax.: - timing of mrs command to power down entry tmrspden tmrspdenmin.: tmod(min) tmrspdenmax.: - odt timings odt high time without write command or with write command and bc4 odth4 odth4min.: 4 nck odth4max.: - odt high time with write command and bl8 odth8 odth8min.: 6 nck odth8max.: - asynchronous rtt turn-on delay (power- down with dll frozen) taonpd 2 8.5 2 8.5 ns asynchronous rtt turn-off delay (power- down with dll frozen) taofpd 2 8.5 2 8.5 ns rtt turn-on taon -250 250 -225 225 ps rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 tck(avg) 7,f rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 tck(avg) 8,f write leveling timings f first dqs/dqs# rising edge after write leveling mode is programmed twlmrd 40 - 40 - nck dqs/dqs# delay after write leveling mode is programmed twldqsen 25 - 25 - nck 3 write leveling setup time from rising ck, ck# crossing to rising dqs, dqs# crossing twls 195 - 165 - ps write leveling hold time from rising dqs, dqs# crossing to ri sing ck, ck# crossing twlh 195 - 165 - ps write leveling output delay twlo 0 9 0 7.5 ns write leveling output error twloe 0 2 0 2 ns 9.3 jitter notes specific note a unit ?tck(avg)? represents the actual tck(avg) of the input clock under operation. unit ?nck ? represents one clock cycle of the input clock, counting the actual clock edges. ex) tm rd=4 [nck] means; if one mode register set command is registered at tm, another mode register set command may be r egistered at tm+4, even if (tm+4-tm) is 4 x tck(avg) + terr(4per), min. specific note b these parameters are measured from a command/address sig nal (cke, cs, ras, cas, we , odt, ba0, a0, a1, etc) transition edge to its respective clock signal (ck/ck) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), et c.), as the setup and hold are relative to the clock signal crossing that latches t he command/address. that is, these parameters should be met whether clock jitter is present or not. specific note c these parameters are measured from a data strobe signal (dqs(l/u), dqs(l/u)) cros sing to its respective clock signal (ck, ck) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc), as
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 60 rev. 00a 04/16/2012 these are relative to the clock signal crossing. that is, thes e parameters should be met whether clock jitter is present or not. specific note d these parameters are measured from a data signal (dm(l/u), dq(l/u)0, dq(l/u)1, etc.) transition edge to its respective data strobe signal (dqs(l/u ), dqs(l/u)) crossing. specific note e for these parameters, the ddr3 sdram device supports tnpa ram [nck] = ru{tparam[ns] / tc k(avg)[ns]}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. fo r example, the device will support tnrp =ru{trp/tck(avg)}, which is in clock cycles, if all input cl ock jitter specifications are met. this means: for ddr3-800 6-6- 6, of which trp = 15ns, the device will suppo rt tnrp = ru{trp/tck(avg)} = 6, as long as the input clock jitter specifications are met, i.e. precharge command at tm and active command at tm +6 is valid even if (tm+6-tm) is less than 15ns due to input clock jitter. specific note f when the device is operated with input clock jitter, this par ameter needs to be derated by t he actual terr(mper), act of the input clock, where 2 <= m <=12. (output der ating are relative to the sdram input clock.) for example, if the measured jitter in to a ddr3-800 sdram has terr(mper),act ,min = -172ps and terr(mper),act,max = 193ps, then tdqsck,min(derated) = tdqsck,min - terr(mper),act,max = -400ps - 193ps = -593ps and tdqsck,max(derated) = tdqsck,max - err(mper),act,min = 400ps + 172ps = 572 ps. similarly, tlz(dq) for ddr3-800 derates to tlz(dq),min(derated) = -800ps - 193ps = -993ps and tlz(dq),max(derated) = 400ps + 172ps = 572ps. (caution on the min/max usage!) note that terr(mper),act,min is the minimum me asured value of terr(nper) where 2 <= n <= 12, and terr(mper),act,max is the maximum measur ed value of terr(nper) where 2 <= n <= 12. specific note g when the device is operated with input clock jitter, this par ameter needs to be derated by t he actual tjit(per),act of the input clock. (output deratings are relati ve to the sdram input clock.) for exampl e, if the measured jitter into a ddr3-800 sdram has tck(avg),act=2500ps, tjit( per),act,min = -72ps and tjit(per),act,max = 93ps, then trpre,min(derated) = trpre,min + tjit(per),act,min = 0.9 x tck(avg),act + tjit(per),act,min = 0.9 x 2500ps - 72ps = 2178ps. similarly, tqh,min(derated) = tqh,min + tjit(per),act,min = 0.38 x tc k(avg),act + tjit(per),act,min = 0.38 x 2500ps - 72ps = 878ps. (caution on the min/max usage!) 9.4 timing parameter notes 1. actual value dependent upon measurement level definitions. 2. commands requiring a locked dll are: read ( and rap) are synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register. 5. value must be rouned-up to next higher integer value. 6. there is no maximum cycle time limit besides t he need to satisfy the refresh interval, trefi. 7. for definition of rtt-on time taon see ?timing parameters?. 8. for definition of rtt-off time taof see ?timing parameters?. 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles are programmed in mr0. 11. the maximum read postamble is bonded by tdqsck(min) plus tqsh(min) on the left side and thz(dqs)max on the right side. 12. output timing deratings are relative to the sdram input cl ock. when the device is operated with input clock jitter, this parameter needs to be derated by tbd. 13. value is only valid for ron34. 14. single ended signal parameter. 15. trefi depends on toper.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 61 rev. 00a 04/16/2012 16. tis(base) and tih(base) values are for 1v/ns cmd/add single-ended slew rate and 2v/ns ck, ck differential slew rate. note for dq and dm signals, vref(dc)=vre fdq(dc). for input only pins except reset, vref(dc)=vrefca(dc). 17. tds(base) and tdh(base) values are for 1v/ns dq single- ended slew rate and 2v/ns dqs, dqs differential slew rate. 18. note for dq and dm signals, vref (dc)=vrefdq(dc). for input only pins except reset, vref(dc)=vrefca(dc). 19. start of internal write transaction is defined as follows: 20. for bl8 (fixed by mrs and on-the-fly) : rising clock edge 4 clock cycles after wl. 21. for bc4 (on-the-fly): rising clock edge 4 clock cycles after wl. 22. for bc4 (fixed by mrs): rising clock edge 2 clock cycles after wl. 19. the maximum preamble is bound by tlz(dqs)max on the left side and tdqsck(max) on the right side. 20. cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down idd spec will not be applied until finishing those operations. 21. although cke is allowed to be registered low after a refresh command once trefpden(min) is satisfied, there are cases where additional time such as txpdll(min) is also required. 22. defined between end of mpr read burst and mrs which reloads mpr or disables mpr function. 23. one zqcs command can effectively correct a minimum of 0.5% (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum se nsitivities specified in the ?output driver voltage and temperature sensitivity? and ?odt voltage and temperature sensitivity? tables. the appropriate interval between zqcs commands can be determined from these tables and other application-specific parameters. 23. one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is subject to in the application, is illustra ted. the interval could be defined by the following formula: zqcorrection / [(tsens x tdriftrate) + (vsens x vdriftrate)] , where tsens = max(drttdt, drondtm) and vsens = ma x(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5%/c, vsens = 0.15%/mv, tdriftrate = 1 c/sec and vd riftrate = 15mv/sec, then the interval between zqcs commands is calculated as 0.5 / [(1.5x1)+(0.15x15)] = 0.133 ? 128ms 24. n = from 13 cycles to 50 cycles. this row defines 38 parameters. 25. tch(abs) is the absolut e instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 26. tcl(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. 27. the tis(base) ac150 specifications are adjusted from t he tis(base) specification by adding an additional 100ps of derating to accommodate for the lower altemate thres hold of 150mv and another 25ps to account for the earlier reference point [(175mv - 150mv) / 1v/ns]. 28. pulse width of a input signal is defined as the widt h between the first crossing of vref(dc) and the consecutive crossing of vref(dc). 29. tdqsl describes the instantaneous differential input low pulse width on dqs - dqs#, as measured from one falling edge to the next consecutive rising edge. 30. tdqsh describes the instantaneous differential input high pulse width on dqs - dqs#, as measured from one rising edge to the next consecutive falling edge. 31. tdqsh,act + tdqsl,act = 1 tck,act ; with txyz,act being the actual measured value of the respective timing parameter in the application. 32. tdsh,act + tdss,act = 1 tck,act ; with txyz,act being t he actual measured value of the respective timing parameter in the application.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 62 rev. 00a 04/16/2012 9.5 address / command setup, hold and derating for all input signals the total tis (setup time) and tih (hold ti me) required is calculated by adding the datasheet tis(base) and tih(base) value to the ? tis and ? tih derating value respectively. example: tis (total setup time) = tis(base) + ? tis setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vih(ac)min. setup (tis) nominal slew rate fo r a falling signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded ?vref(dc) to ac region?, use nominal slew ra te for derating value . if the actual signal is later than the nominal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to vref (d c) level is used for derating value. hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref(dc). hold (tih) no minal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded ?dc to vref(dc) region?, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref (d c) level is used for derating value. for a valid transition the input signal has to remain above/ below vih/il(ac) for some time tvac. although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition, a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rates in between the values listed in table 69, the deratin g values may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. 9.5.1 add/cmd setup and hold base-values for 1v/ns symbol reference ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units tis(base) ac175 vih/l(ac) 200 125 65 45 ps tis(base) ac150 vih/l(ac) 350 275 190 170 ps tih(base) dc100 vih/l(dc) 275 200 140 120 ps notes: 1. (ac/dc referenced for 1v/ns address/command slew rate and 2 v/ns differential ck-ck# slew rate) 2. the tis(base) ac150 specifications ar e adjusted from the tis(base) ac175 specif ication by adding an additional 125 ps for dd r3-800/1066 or 100ps for ddr3-1333/1600 of derating to accommodate for the lower alternate threshold of 150 mv and another 25 ps to account f or the earlier reference point [(175 mv - 150 mv) / 1 v/ns].
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 63 rev. 00a 04/16/2012 9.5.2 derating values ddr3 -800/1066/1333/1600 tis/tih - ac/ dc based ac175 threshold tis, tih derating in [ps] ac/dc based ac175 threshold -> vih(ac)=vref(dc )+175mv, vil(ac)=vref(dc)-175mv ck,ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmaddd/ slew rate v/ns 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 -2 -4 -2 -4 -2 -4 6 4 14 12 22 20 30 30 38 46 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 18 14 26 24 34 40 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 - 17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 - 60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10 9.5.3 derating values ddr3-800/ 1066/1333/1600 tis/tih - ac/dc b ased ? alternate ac150 threshold tis, tih derating in [ps] ac/dc based alternate ac150 threshold -> vih(ac)=v ref(dc)+150mv, vil(ac)=vref(dc)-150mv ck,ck# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih caddmd/ slew rate v/ns 2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 9.5.4 required time tvac above vih(ac ) {below vil(ac)} for valid transition slew rate [v/ns] tvac @ ac175 [ps] tvac @ ac150 [ps] min max min max > 2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - < 0.5 0 - 150 -
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 64 rev. 00a 04/16/2012 9.5.5 address / command setup, hold and derating 9.6.5.1 nominal slew rate and tvac for setup time tis(le ft) and hold time t dh(right) ? add/cmd with respect to clock 9.6.5.2 tangent line for setup time tis(left) and hold time tih(right) - add/cmd with respect to clock vref to ac re g ion vref to dc vref to ac re g ion vref to ac re g ion ck# ck v ddq vih(ac)min vih(dc)min vref(dc) vil(dc)max vil(ac)max normal slew rate normal slew rate tis tih tvac tvac tis tih v ss ? tf ? tf setup slew rate @ rising signal = [vih(ac)min-vref(dc)] / tr ck# ck v ddq vih(ac)min vih(dc)min vref(dc) vil(dc)max vil(ac)max normal slew rate normal slew rate tis tih tvac tis tih v ss ? ? tr hold slew rate @ falling signal = [vih(dc)min-vref(dc)] / tf ck# ck v ddq vih(ac)min vih(dc)min vref(dc) vil(dc)max vil(ac)max normal slew rate normal slew rate tis tih tvac tvac tis tih v ss ? tf ? tr setup slew rate @ rising signal = tangent line [vih(ac)min-vref(dc)] / tr setup slew rate @ falling signal = tangent line [vref(dc)-vil(ac)max] / tf tangent line tangent line ck# ck v ddq vih(ac)min vih(dc)min vref(dc) vil(dc)max vil(ac)max normal slew rate normal slew rate tis tih tis tih v ss ? tf hold slew rate @ rising signal = tangent line [vref(dc)-vil(dc)max] / tr tangent line tangent line ? tf
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 65 rev. 00a 04/16/2012 9.6 data setup, hold and slew rate derating for all input signals the total tds (setup time) and tdh (hol d time) required is calculated by adding the data sheet tds(base) and tdh(base) value (see table 72) to the ? tds and ? tdh (see table 73) derating value respectively. example: tds (total setup time) = tds(base) + ? tds. setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of v ih(ac) min. setup (tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of vil(ac) max. if t he actual signal is always earlier than the nominal slew rate line between shaded ?vref(dc) to ac region?, use nominal slew rate for derating value. if the actual signal is later than the nominal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to vref(d c) level is used for derating value. hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the la st crossing of vil(dc) max and the first crossing of vref(dc) . hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc) min and the first crossing of vref(dc) . if the actual signal is always later than the nominal slew rate line between shaded ?dc level to vref(dc) region?, use nomi nal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value. for a valid transition the input signal has to rema in above/below vih/il(ac) for some time tvac. although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and re ach vih/il(ac) . for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. 9.6.1 data setup and hold base-values symbol reference ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units tds(base) ac175 vih/l(ac) 75 25 - - ps tds(base) ac150 vih/l(ac) 125 75 30 10 ps tdh(base) dc100 vih/l(dc) 150 100 65 45 ps note: (ac/dc referenced for 1v/ns dq-slew rate and 2 v/ns dqs slew rate)
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 66 rev. 00a 04/16/2012 9.6.2 derating values ddr3 -800/1066 tds/tdh - (ac175) a tds, a dh derating in [ps] ac/dc based 1 dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns a tds a tdh a tds a tdh a tds a tdh a tds a tdh a tds a tdh a tds a tdh a tds a tdh a tds a tdh dq slew rate v/ns 2.0 88 50 88 50 88 50 - - - - - - - - - - 1.5 59 34 59 34 59 34 67 42 - - - - - - - - 1.0 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - -2 -4 -2 -4 6 4 14 12 22 20 - - - - 0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - - 0.7 - - - - - - -3 -8 5 0 13 8 21 18 29 34 0.6 - - - - - - - - -1 -10 7 -2 15 8 23 24 0.5 - - - - - - - - - - -11 -16 -2 -6 5 10 0.4 - - - - - - - - - - - - -30 -26 -22 -10 note 1. cell contents shaded in red are defined as ?not supported?. 9.6.3 derating values for ddr3-800 /1066/1333/1600 tds/tdh - (ac150) a tds, a dh derating in [ps] ac/dc based 1 dqs, dqs# differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1.0 v/ns a tds a tdh a tds a tdh a tds a tdh a tds a tdh a tds a tdh a tds a tdh a tds a tdh a tds a tdh dq slew rate v/ns 2.0 75 50 75 50 75 50 - - - - - - - - - - 1.5 50 34 50 34 50 34 58 42 - - - - - - - - 1.0 0 0 0 0 0 0 8 8 16 16 - - - - - - 0.9 - - 0 -4 0 -4 8 4 16 12 24 20 - - - - 0.8 - - - - 0 -10 8 -2 16 6 24 14 32 24 - - 0.7 - - - - - - 8 -8 16 0 24 8 32 18 40 34 0.6 - - - - - - - - 15 -10 23 -2 31 8 39 24 0.5 - - - - - - - - - - 14 -16 22 -6 30 10 0.4 - - - - - - - - - - - - 7 -26 15 -10 note 1. cell contents shaded in red are defined as ?not supported?. 9.6.4 required time tvac above vih(ac ) {below vil(ac)} for valid transition slew rate [v/ns] ddr3-800/1066 (ac175) ddr3-800/1066/1333/1600 (ac150) slew rate [v/ns] tvac [ps] tvac [ps] min max min max > 2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 155 - < 0.5 0 - 150 -
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 67 rev. 00a 04/16/2012 9.6.5 data setup, hold and slew rate derating 9.6.5.1 nominal slew rate and tvac for setup time tds(left) and hold time t dh (right) - dq with re spect to strobe 9.6.5.2 tangent line for setup time tds(left) and hold time tdh(right) - dq with respect to strobe vref to ac re g ion vref to dc re g ion dqs# dqs v ddq vih(ac)min vih(dc)min vref(dc) vil(dc)max vil(ac)max normal slew rate normal slew rate tds tdh tvac tvac tds tdh vref to ac re g ion v ss ? tf ? tf setup slew rate @ rising signal = [vih(ac)min-vref(dc)] / tr dqs# dqs v ddq vih(ac)min vih(dc)min vref(dc) vil(dc)max vil(ac)max normal slew rate normal slew rate tds tdh tvac tds tdh v ss ? tr ? tr hold slew rate @ falling signal = [vih(dc)min-vref(dc)] / tf dqs# dqs v ddq vih(ac)min vih(dc)min vref(dc) vil(dc)max vil(ac)max normal slew rate normal slew rate tds tdh tvac tvac tds tdh vref to ac re g ion v ss ? tf ? tr setup slew rate @ rising signal = tangent line [vih(ac)min-vref(dc)] / tr setup slew rate @ falling signal = tangent line [vref(dc)-vil(ac)max] / tf tangent line tangent line dqs# dqs v ddq vih(ac)min vih(dc)min vref(dc) vil(dc)max vil(ac)max normal slew rate normal slew rate tds tdh tds tdh v ss ? tf hold slew rate @ rising signal = tangent line [vref(dc)-vil(dc)max] / tr tangent line tangent line ? tf
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 68 rev. 00a 04/16/2012 ordering information 64mx16 - commercial range: (0c ? t c ? 95c) data rate cl-trcd-trp order part no. package 1066mt/s 7-7-7 IS43TR16640A - 187fbl 96-ball fbga,lead-free 1333mt/s 8-8-8 IS43TR16640A - 15gbl 96-ball fbga,lead-free 1333mt/s 9-9-9 IS43TR16640A -15hbl 96-ball fbga,lead-free 1600mt/s 10-10-10 IS43TR16640A -125jbl 96-ball fbga,lead-free 1600mt/s 11-11-11 IS43TR16640A -125kbl 96-ball fbga,lead-free 64mx16 - industrial range: (?40c ? t c ? 95c) data rate cl-trcd-trp order part no. package 1066mt/s 7-7-7 IS43TR16640A - 187fbli 96-ball fbga,lead-free 1333mt/s 8-8-8 IS43TR16640A - 15gbli 96-ball fbga,lead-free 1333mt/s 9-9-9 IS43TR16640A - 15hbli 96-ball fbga,lead-free 1600mt/s 10-10-10 IS43TR16640A - 125jbli 96-ball fbga,lead-free 1600mt/s 11-11-11 IS43TR16640A -125kbli 96-ball fbga,lead-free 64mx16 ? automotive, a1 range: (?40c ? t c ? 95c) data rate cl-trcd-trp order part no. package 1066mt/s 7-7-7 is46tr16640a -187f bla1 96-ball fbga,lead-free 1333mt/s 8-8-8 is46tr16640a -15g bla1 96-ball fbga,lead-free 1333mt/s 9-9-9 is46tr16640a -15h bla1 96-ball fbga,lead-free 1600mt/s 10-10-10 is46tr16640a - 125jbla1 96-ball fbga,lead-free 1600mt/s 11-11-11 is46tr16640a -125kbla1 96-ball fbga,lead-free 64mx16 ? automotive, a2 range: (?40c ? t c ? 105c) data rate cl-trcd-trp order part no. package 1066mt/s 7-7-7 is46tr16640a -187f bla2 96-ball fbga,lead-free 1333mt/s 8-8-8 is46tr16640a -15g bla2 96-ball fbga,lead-free 1333mt/s 9-9-9 is46tr16640a -15h bla2 96-ball fbga,lead-free 1600mt/s 10-10-10 is46tr16640a - 125jbla2 96-ball fbga,lead-free 1600mt/s 11-11-11 is46tr16640a -125kbla2 96-ball fbga,lead-free note: contact issi for availability of options.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 69 rev. 00a 04/16/2012 ordering information 128mx8 - commercial range: (0c ? t c ? 95c) data rate cl-trcd-trp order part no. package 1066mt/s 7-7-7 is43tr81280a - 187fbl 78-ball fbga,lead-free 1333mt/s 8-8-8 is43tr81280a - 15gbl 78-ball fbga,lead-free 1333mt/s 9-9-9 is43tr81280a -15hbl 78-ball fbga,lead-free 1600mt/s 10-10-10 is43tr81280a -125jbl 78-ball fbga,lead-free 1600mt/s 11-11-11 is43tr81280a -125kbl 78-ball fbga,lead-free 128mx8 - industrial range: (?40c ? t c ? 95c) data rate cl-trcd-trp order part no. package 1066mt/s 7-7-7 is43tr81280a - 187fbli 78-ball fbga,lead-free 1333mt/s 8-8-8 is43tr81280a - 15gbli 78-ball fbga,lead-free 1333mt/s 9-9-9 is43tr81280a - 15hbli 78-ball fbga,lead-free 1600mt/s 10-10-10 is43tr81280a - 125jbli 78-ball fbga,lead-free 1600mt/s 11-11-11 is43tr81280a -125kbli 78-ball fbga,lead-free 128mx8 ? automotive, a1 range: (?40c ? t c ? 95c) data rate cl-trcd-trp order part no. package 1066mt/s 7-7-7 is46tr81280a -187f bla1 78-ball fbga,lead-free 1333mt/s 8-8-8 is46tr81280a -15g bla1 78-ball fbga,lead-free 1333mt/s 9-9-9 is46tr81280a -15h bla1 78-ball fbga,lead-free 1600mt/s 10-10-10 is46tr81280a - 125jbla1 78-ball fbga,lead-free 1600mt/s 11-11-11 is46tr81280a -125kbla1 78-ball fbga,lead-free 128mx8 ? automotive, a2 range: (?40c ? t c ? 105c) data rate cl-trcd-trp order part no. package 1066mt/s 7-7-7 is46tr81280a -187f bla2 78-ball fbga,lead-free 1333mt/s 8-8-8 is46tr81280a -15g bla2 78-ball fbga,lead-free 1333mt/s 9-9-9 is46tr81280a -15h bla2 78-ball fbga,lead-free 1600mt/s 10-10-10 is46tr81280a - 125jbla2 78-ball fbga,lead-free 1600mt/s 11-11-11 is46tr81280a -125kbla2 78-ball fbga,lead-free note: contact issi for availability of options.
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 70 rev. 00a 04/16/2012
IS43TR16640A, is43tr81280a integrated silicon solution, inc. ? www.issi.com ? 71 rev. 00a 04/16/2012

▲Up To Search▲

Price & Availability of IS43TR16640A

	To Download IS43TR16640A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .